APL5934DKAI-TRG

@@ -63,6 +63,18 @@   <smd name="7" x="2.4800" y="0.6350" dx="1.9400" dy="0.6000" layer="1"/>   <smd name="8" x="2.4800" y="1.9050" dx="1.9400" dy="0.6000" layer="1"/>   <smd name="9" x="0.0000" y="-0.0000" dx="2.6200" dy="3.5100" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -71,7 +83,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.475" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.475" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="APL5934DKAI-TRG">@@ -111,7 +123,13 @@         <connect gate="G$1" pin="NC" pad="5"/>         <connect gate="G$1" pin="GND@2" pad="9"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="APL5934DKAI-TRG" constant="no"/>+          <attribute name="MANUFACTURER" value="Anpec Elec" constant="no"/>+          <attribute name="LCSC_PN" value="C691401" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>

@@ -26,7 +26,9 @@       "model_3d_step": "apl5934dkai-trg.step",       "lbr": "apl5934dkai-trg.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C691401"+    },     "pins": [       {         "number": "1",@@ -38,19 +40,19 @@         "number": "2",         "name": "EN",         "type": "input",-        "description": "Active-high enable control pin. Holding EN below the enable threshold (~0.8V typical) shuts down the output; re-enabling triggers a new soft-start cycle. An internal ~3µA pull-low current pulls EN low when left open (initial-off for the /D variant), disabling the regulator by default."+        "description": "Active-high enable control pin. Holding EN below the enable threshold (~0.8V typical) shuts down the output; re-enabling triggers a new soft-start cycle. An internal ~3\u00b5A pull-low current pulls EN low when left open (initial-off for the /D variant), disabling the regulator by default."       },       {         "number": "3",         "name": "VIN",         "type": "power_in",-        "description": "Main power supply input (1.2V ~ 5.5V) used for voltage conversion to VOUT. A ≥10µF decoupling capacitor is recommended close to this pin to filter noise and improve transient response. The voltage on VIN is monitored by the Power-On-Reset circuit (rising VIN POR threshold ~0.9V)."+        "description": "Main power supply input (1.2V ~ 5.5V) used for voltage conversion to VOUT. A \u226510\u00b5F decoupling capacitor is recommended close to this pin to filter noise and improve transient response. The voltage on VIN is monitored by the Power-On-Reset circuit (rising VIN POR threshold ~0.9V)."       },       {         "number": "4",         "name": "VCNTL",         "type": "power_in",-        "description": "Bias voltage input for the internal control circuitry (3.0V ~ 5.5V, +5V recommended). A 0.1µF decoupling capacitor is typically connected near this pin. VCNTL is also monitored by the Power-On-Reset circuit (rising VCNTL POR threshold ~2.7V)."+        "description": "Bias voltage input for the internal control circuitry (3.0V ~ 5.5V, +5V recommended). A 0.1\u00b5F decoupling capacitor is typically connected near this pin. VCNTL is also monitored by the Power-On-Reset circuit (rising VCNTL POR threshold ~2.7V)."       },       {         "number": "5",@@ -62,13 +64,13 @@         "number": "6",         "name": "VOUT",         "type": "power_out",-        "description": "Regulated output pin (0.8V to VIN−VDROP, up to 3A continuous / 4A peak). Requires a minimum 10µF output capacitor (MLCC applicable) for stability and transient response; total COUT scales with load per the datasheet (8-1100µF at 3A). During shutdown an internal ~85Ω pull-down MOSFET quickly discharges VOUT."+        "description": "Regulated output pin (0.8V to VIN\u2212VDROP, up to 3A continuous / 4A peak). Requires a minimum 10\u00b5F output capacitor (MLCC applicable) for stability and transient response; total COUT scales with load per the datasheet (8-1100\u00b5F at 3A). During shutdown an internal ~85\u03a9 pull-down MOSFET quickly discharges VOUT."       },       {         "number": "7",         "name": "FB",         "type": "input",-        "description": "Voltage feedback pin. Connect to the tap of an external resistor divider from VOUT to set the output voltage against the 0.8V internal reference (VOUT = 0.8V × (1 + R1/R2)). FB input current is ±100nA max."+        "description": "Voltage feedback pin. Connect to the tap of an external resistor divider from VOUT to set the output voltage against the 0.8V internal reference (VOUT = 0.8V \u00d7 (1 + R1/R2)). FB input current is \u00b1100nA max."       },       {         "number": "8",