component
AP7167-SPG-13
Public Made by Adomby adom
Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+12−9@@ -32,25 +32,25 @@ "number": "1", "name": "IN", "type": "power_in",- "description": "Voltage input pin. Pin 1 and pin 2 must be tied together externally. Bypass to ground through at least a 1\u00b5F ceramic capacitor. Input range 2.2V to 5.5V."+ "description": "Voltage input pin. Pin 1 and pin 2 must be tied together externally. Bypass to ground through at least a 1µF ceramic capacitor. Input range 2.2V to 5.5V." }, { "number": "2", "name": "IN", "type": "power_in",- "description": "Voltage input pin. Pin 1 and pin 2 must be tied together externally. Bypass to ground through at least a 1\u00b5F ceramic capacitor."+ "description": "Voltage input pin. Pin 1 and pin 2 must be tied together externally. Bypass to ground through at least a 1µF ceramic capacitor." }, { "number": "3", "name": "POK", "type": "output",- "description": "Power-OK output, active-high open-drain. Requires an external pull-up resistor (recommended 10k\u03a9-1M\u03a9) to a rail \u2264 5.5V. Sink current up to 4mA. Asserts when FB (or OUT) rises above ~92% of Vref. POK must be disconnected from IN pin."+ "description": "Power-OK output, active-high open-drain. Requires an external pull-up resistor (recommended 10kΩ-1MΩ) to a rail ≤ 5.5V. Sink current up to 4mA. Asserts when FB (or OUT) rises above ~92% of Vref. POK must be disconnected from IN pin." }, { "number": "4", "name": "EN", "type": "input",- "description": "Enable input, active high. Vih \u2265 1.4V enables the regulator; Vil \u2264 0.4V shuts it down. Tie to IN to keep the regulator always on. Input leakage \u2264 1\u00b5A."+ "description": "Enable input, active high. Vih ≥ 1.4V enables the regulator; Vil ≤ 0.4V shuts it down. Tie to IN to keep the regulator always on. Input leakage ≤ 1µA." }, { "number": "5",@@ -62,25 +62,25 @@ "number": "6", "name": "FB", "type": "input",- "description": "Output feedback input to the internal error amplifier. Regulates to Vref = 0.8V typical. Set output via external divider: Vout = Vref \u00d7 (1 + R1/R2); keep R2 < 250k\u03a9 for reference stability. FB leakage \u2264 1\u00b5A."+ "description": "Output feedback input to the internal error amplifier. Regulates to Vref = 0.8V typical. Set output via external divider: Vout = Vref × (1 + R1/R2); keep R2 < 250kΩ for reference stability. FB leakage ≤ 1µA." }, { "number": "7", "name": "OUT", "type": "power_out",- "description": "Voltage output pin. Pin 7 and pin 8 must be tied together externally. Bypass to ground with at least a 4.7\u00b5F ceramic capacitor. Output range 0.8V to 5.0V, up to 1.2A."+ "description": "Voltage output pin. Pin 7 and pin 8 must be tied together externally. Bypass to ground with at least a 4.7µF ceramic capacitor. Output range 0.8V to 5.0V, up to 1.2A." }, { "number": "8", "name": "OUT", "type": "power_out",- "description": "Voltage output pin. Pin 7 and pin 8 must be tied together externally. Bypass to ground with at least a 4.7\u00b5F ceramic capacitor."+ "description": "Voltage output pin. Pin 7 and pin 8 must be tied together externally. Bypass to ground with at least a 4.7µF ceramic capacitor." }, { "number": "EP", "name": "EP", "type": "passive",- "description": "Exposed thermal pad on package underside. Primary conduction path for heat to the PCB; connect to a copper thermal plane. May be tied to GND or left floating, but should be soldered to copper for thermal performance (\u03b8JA \u2248 27\u00b0C/W)."+ "description": "Exposed thermal pad on package underside. Primary conduction path for heat to the PCB; connect to a copper thermal plane. May be tied to GND or left floating, but should be soldered to copper for thermal performance (θJA ≈ 27°C/W)." } ], "provenance": {@@ -144,5 +144,8 @@ "docs/ap7167-spg-13-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }