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AP7167-SPG-13
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Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+49@@ -0,0 +1,49 @@+# AP7167-SPG-13++**Diodes Incorporated** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP++AP7167-SPG-13 from Diodes Incorporated, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN | power_in | Voltage input pin. Pin 1 and pin 2 must be tied together externally. Bypass to ground through at least a 1µF ceramic capacitor. Input range 2.2V to 5.5V. |+| 2 | IN | power_in | Voltage input pin. Pin 1 and pin 2 must be tied together externally. Bypass to ground through at least a 1µF ceramic capacitor. |+| 3 | POK | output | Power-OK output, active-high open-drain. Requires an external pull-up resistor (recommended 10kΩ-1MΩ) to a rail ≤ 5.5V. Sink current up to 4mA. Asserts when FB (or OUT) rises above ~92% of Vref. POK must be disconnected from IN pin. |+| 4 | EN | input | Enable input, active high. Vih ≥ 1.4V enables the regulator; Vil ≤ 0.4V shuts it down. Tie to IN to keep the regulator always on. Input leakage ≤ 1µA. |+| 5 | GND | power_in | Ground reference for the regulator. |+| 6 | FB | input | Output feedback input to the internal error amplifier. Regulates to Vref = 0.8V typical. Set output via external divider: Vout = Vref × (1 + R1/R2); keep R2 < 250kΩ for reference stability. FB leakage ≤ 1µA. |+| 7 | OUT | power_out | Voltage output pin. Pin 7 and pin 8 must be tied together externally. Bypass to ground with at least a 4.7µF ceramic capacitor. Output range 0.8V to 5.0V, up to 1.2A. |+| 8 | OUT | power_out | Voltage output pin. Pin 7 and pin 8 must be tied together externally. Bypass to ground with at least a 4.7µF ceramic capacitor. |+| EP | EP | passive | Exposed thermal pad on package underside. Primary conduction path for heat to the PCB; connect to a copper thermal plane. May be tied to GND or left floating, but should be soldered to copper for thermal performance (θJA ≈ 27°C/W). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Diodes Incorporated |+| Package | SOIC-8-EP |+| Category | PMIC |+| Pins | 9 |++## Ordering variants++- `AP7167-SPG-13`+- `AP7167-SPG-13FNG-7`++## CAD (KiCad official)++- Symbol: `AP7167-SPG-13`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`+- 3D model: SOIC-8-EP (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/AP7167-SPG-13.pdf) (14 pp, sha256 `5ff6f0abf2d05446`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ap7167-spg-13-datasheet.pdf)
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