ap64500sp-13: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
ap64500sp-13: laser-etched CAD + chip hero (factory 2.0.0 backfill)
ap64500sp-13: publish the laser-etched STEP alongside the bare one
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <te…
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> Diodes_SO-8EP (ep_dropped, 8 pins; datasheet EP 3.502x2.613mm, land 2.613x3.…
ap64500sp-13: factory component page (tier=lcsc)
Initial commit: component/ap64500sp-13