component
AO4805
Public Made by Adomby adom
Alpha & Omega Semiconductor FET, MOSFET Arrays, SOIC-8. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.
← Commit history
Publish 0.1.1
8 files changed
+392−63
README.md+12−10@@ -4,20 +4,20 @@ **Alpha & Omega Semiconductor** · FET, MOSFET Arrays · SOIC-8 -AO4805 from Alpha & Omega Semiconductor, in a SOIC-8. Symbol, footprint and 3D model are the ones used on Adom board designs (3D model: KiCad library 3D model SOIC-8_3.9x4.9mm_P1.27mm (CC-BY-SA 4.0 with the KiCad library exception)). Pin functions are extracted from the manufacturer datasheet with page references. **Staged for validation: see the open items in the verification log above.**+AO4805 from Alpha & Omega Semiconductor, in a SOIC-8. Symbol, footprint and 3D model are the ones used on Adom board designs (3D model: KiCad library 3D model SOIC-8_3.9x4.9mm_P1.27mm (CC-BY-SA 4.0 with the KiCad library exception)). Pin functions are extracted from the manufacturer datasheet with page references. ## Pinout | Pin | Name | Type | Function | |---|---|---|---|-| 1 | S2 | passive | Source of P-channel MOSFET #2. Connected to the source terminal of the second P-channel MOSFET die inside the dual package. [datasheet p.1] |-| 2 | G2 | input | Gate of P-channel MOSFET #2. Gate threshold voltage VGS(th) = -1.7V to -2.8V (typical -2.3V). Maximum VGS = ±25V. [datasheet p.1] |-| 3 | S1 | passive | Source of P-channel MOSFET #1. Connected to the source terminal of the first P-channel MOSFET die inside the dual package. [datasheet p.1] |-| 4 | G1 | input | Gate of P-channel MOSFET #1. Gate threshold voltage VGS(th) = -1.7V to -2.8V (typical -2.3V). Maximum VGS = ±25V. [datasheet p.1] |-| 5 | D1 | passive | Drain of P-channel MOSFET #1. Pins 5 and 6 are tied together internally for current handling and thermal performance. Drain-Source breakdown voltage BVDSS = -30V. [datasheet p.1] |-| 6 | D1 | passive | Drain of P-channel MOSFET #1. Pins 5 and 6 are tied together internally for current handling and thermal performance. Drain-Source breakdown voltage BVDSS = -30V. [datasheet p.1] |-| 7 | D2 | passive | Drain of P-channel MOSFET #2 (second drain lead). Pins 7 and 8 are tied together internally for current handling and thermal performance. [datasheet p.1] |-| 8 | D2 | passive | Drain of P-channel MOSFET #2 (second drain lead). Pins 7 and 8 are tied together internally for current handling and thermal performance. [datasheet p.1] |+| 1 | S2 | passive | Source of P-channel MOSFET 2 (S2), per the SOIC-8 top-view pinout and the internal schematic. [datasheet p.1] |+| 2 | G2 | input | Gate of P-channel MOSFET 2 (G2). Gate-source voltage ±25 V absolute maximum [datasheet p.1]; gate threshold VGS(th) -1.7 V min, -2.3 V typ, -2.8 V max at ID = -250 µA. [datasheet p.2] |+| 3 | S1 | passive | Source of P-channel MOSFET 1 (S1), per the SOIC-8 top-view pinout and the internal schematic. [datasheet p.1] |+| 4 | G1 | input | Gate of P-channel MOSFET 1 (G1). Gate-source voltage ±25 V absolute maximum [datasheet p.1]; gate threshold VGS(th) -1.7 V min, -2.3 V typ, -2.8 V max at ID = -250 µA. [datasheet p.2] |+| 5 | D1 | passive | Drain of P-channel MOSFET 1 (D1); pins 5 and 6 are both D1. Drain-source voltage -30 V absolute maximum. [datasheet p.1] |+| 6 | D1 | passive | Drain of P-channel MOSFET 1 (D1); pins 5 and 6 are both D1. Drain-source voltage -30 V absolute maximum. [datasheet p.1] |+| 7 | D2 | passive | Drain of P-channel MOSFET 2 (D2); pins 7 and 8 are both D2. Drain-source voltage -30 V absolute maximum. [datasheet p.1] |+| 8 | D2 | passive | Drain of P-channel MOSFET 2 (D2); pins 7 and 8 are both D2. Drain-source voltage -30 V absolute maximum. [datasheet p.1] | ## Key specifications @@ -28,6 +28,8 @@ AO4805 from Alpha & Omega Semiconductor, in a SOIC-8. Symbol, footprint and 3D m | Category | Transistors/Thyristors | | Pins | 8 | | LCSC | C38943 |+| Mouser | Not carried |+| DigiKey | 785-1055-2-ND | | Distributor summary (LCSC listing, not datasheet) | -55℃~+150℃ 18mΩ@10V 2 P-Channel 2.6nF 2.8V 2W 3.6pF 30V 39nC@10V 9A SOIC-8 MOSFETs ROHS | ## CAD@@ -40,7 +42,7 @@ AO4805 from Alpha & Omega Semiconductor, in a SOIC-8. Symbol, footprint and 3D m ## Provenance -- **Datasheet:** [Alpha & Omega Semiconductor datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175825766977536) (sha256 `d5ab4cd887b7c167`, retrieved 2026-10-09, tier: lcsc)+- **Datasheet:** [Alpha & Omega Semiconductor AO4805 datasheet](https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf) (Rev 7.1, March 2024, sha256 `b7592fe0daec26e8`, retrieved 2026-10-27, tier: mfr) - **CAD:** Footprint and symbol as used on Adom board designs; 3D model: KiCad library 3D model SOIC-8_3.9x4.9mm_P1.27mm (CC-BY-SA 4.0 with the KiCad library exception). - **Pins:** KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7).
ao4805-hero.glbadded⋯ 1 unchanged line ⋯
ao4805-hero.overlay.jsonadded+260@@ -0,0 +1,260 @@+{+ "spec": "adom-hero 1.4",+ "mpn": "AO4805",+ "kind": "component + footprint reference art",+ "board_use": false,+ "plane_z_mm": -0.02,+ "units": "metre",+ "upAxis": "Z",+ "layers": {+ "pad_outlines": {+ "material": "Footprint pads - teal dashed outlines - 50 percent opacity",+ "rgba": [+ 0.0,+ 0.902,+ 0.863,+ 0.5+ ],+ "pads": 8,+ "span_mm": 6.9,+ "dash_mm": 0.1725,+ "gap_mm": 0.1035,+ "pad_stroke_mm": 0.0414+ },+ "silkscreen": {+ "material": "Silkscreen reference lines - 30 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.3+ ],+ "footprint_items": 7,+ "pin1": {+ "source": "footprint silkscreen",+ "pad": "1"+ }+ },+ "signal_names": {+ "material": "Signal names - 50 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.5+ ],+ "font": "DejaVu Sans Mono",+ "labels": 8,+ "sides": "top + mirrored underside (single-sided)",+ "fallback_to_pad_number": 0+ }+ },+ "align": {+ "ok": true,+ "centre_offset_mm": 0.0,+ "tolerance_mm": 0.552,+ "orientation_flipped": false,+ "contacts_bbox_mm": [+ -3.0,+ 3.0,+ -2.11,+ 2.11+ ],+ "pads_bbox_mm": [+ -3.45,+ 3.45,+ -2.205,+ 2.205+ ],+ "seating_z_mm": 0.0+ },+ "sources": {+ "glb": "ao4805-etched.glb",+ "glb_sha256": "b402468cec53fa823a838f2291342dc92fe42e11931dc580cdb438c0066e33be",+ "footprint": "ao4805.kicad_mod",+ "footprint_sha256": "5be6a82529ce759fd0363b535bf4a2856612f5ef4a6007e670d74f5d8977a470",+ "pins": "page.json component.pins",+ "pins_sha256": "2c1ae677daff467724c8773d097fb30dd154792b8c70fd42f76adbabd82fd91c"+ },+ "generator": "adom-wiki 1.8.0 (component_hero)",+ "labels": [+ {+ "pad": "1",+ "text": "S2",+ "x": -3.6,+ "y": -1.905,+ "align": "right",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "2",+ "text": "G2",+ "x": -3.6,+ "y": -0.635,+ "align": "right",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "3",+ "text": "S1",+ "x": -3.6,+ "y": 0.635,+ "align": "right",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "4",+ "text": "G1",+ "x": -3.6,+ "y": 1.905,+ "align": "right",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "5",+ "text": "D1",+ "x": 3.6,+ "y": 1.905,+ "align": "left",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "6",+ "text": "D1",+ "x": 3.6,+ "y": 0.635,+ "align": "left",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "7",+ "text": "D2",+ "x": 3.6,+ "y": -0.635,+ "align": "left",+ "vertical": false,+ "h": 0.6+ },+ {+ "pad": "8",+ "text": "D2",+ "x": 3.6,+ "y": -1.905,+ "align": "left",+ "vertical": false,+ "h": 0.6+ }+ ],+ "pads": [+ {+ "number": "1",+ "shape": "roundrect",+ "center_mm": [+ -2.475,+ -1.905+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "2",+ "shape": "roundrect",+ "center_mm": [+ -2.475,+ -0.635+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "3",+ "shape": "roundrect",+ "center_mm": [+ -2.475,+ 0.635+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "4",+ "shape": "roundrect",+ "center_mm": [+ -2.475,+ 1.905+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "5",+ "shape": "roundrect",+ "center_mm": [+ 2.475,+ 1.905+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "6",+ "shape": "roundrect",+ "center_mm": [+ 2.475,+ 0.635+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "7",+ "shape": "roundrect",+ "center_mm": [+ 2.475,+ -0.635+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ },+ {+ "number": "8",+ "shape": "roundrect",+ "center_mm": [+ 2.475,+ -1.905+ ],+ "size_mm": [+ 1.95,+ 0.6+ ],+ "rot": 0.0+ }+ ]+}
ao4805.lbr+1−1@@ -145,7 +145,7 @@ <technology name=""> <attribute name="MPN" value="AO4805" constant="no"/> <attribute name="MANUFACTURER" value="Alpha & Omega Semiconductor" constant="no"/>- <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175825766977536" constant="no"/>+ <attribute name="DATASHEET" value="https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf" constant="no"/> <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/ao4805" constant="no"/> <attribute name="DIGIKEY_PN" value="785-1055-2-ND" constant="no"/> <attribute name="LCSC_PN" value="C38943" constant="no"/>
docs/ao4805-datasheet.pdf⋯ 1 unchanged line ⋯
package.json+22−25@@ -1,13 +1,12 @@ { "slug": "ao4805",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "tags": [ "component", "transistors/thyristors", "ao4805",- "board-derived",- "staged-for-validation"+ "board-derived" ], "dependencies": {}, "hero": {@@ -27,8 +26,8 @@ "ao4805.lbr", "docs/hero.png", "docs/ao4805-datasheet.pdf",- "viewers/symbol.html",- "viewers/footprint.html"+ "ao4805-hero.glb",+ "ao4805-hero.overlay.json" ], "component": { "mpn": "AO4805",@@ -37,12 +36,12 @@ "pin_count": 8, "category": "Transistors/Thyristors", "subcategory": "FET, MOSFET Arrays",- "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175825766977536",+ "datasheet": "https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf", "parts": { "symbol": "ao4805.kicad_sym", "footprint": "ao4805.kicad_mod",- "model_3d": "ao4805-etched.glb",- "model_3d_plain": "ao4805.glb",+ "model_3d": "ao4805-hero.glb",+ "model_3d_plain": "ao4805-etched.glb", "model_3d_step": "ao4805-etched.step", "model_3d_step_plain": "ao4805.step", "lbr": "ao4805.lbr"@@ -53,7 +52,7 @@ "url": "https://www.digikey.com/en/products/detail/alpha-omega-semiconductor-inc/AO4805/1855827" }, "mouser": false,- "mouser_note": "2026-10-09: no exact-MPN listing for AO4805 found via the mouser API.",+ "mouser_note": "Not carried: searched AO4805 on 2026-10-09 and 2026-10-27 (Mouser returns no Alpha & Omega listing).", "lcsc": { "part": "C38943", "url": "https://www.lcsc.com/product-detail/C38943.html"@@ -64,49 +63,49 @@ "number": "1", "name": "S2", "type": "passive",- "description": "Source of P-channel MOSFET #2. Connected to the source terminal of the second P-channel MOSFET die inside the dual package. [datasheet p.1]"+ "description": "Source of P-channel MOSFET 2 (S2), per the SOIC-8 top-view pinout and the internal schematic. [datasheet p.1]" }, { "number": "2", "name": "G2", "type": "input",- "description": "Gate of P-channel MOSFET #2. Gate threshold voltage VGS(th) = -1.7V to -2.8V (typical -2.3V). Maximum VGS = ±25V. [datasheet p.1]"+ "description": "Gate of P-channel MOSFET 2 (G2). Gate-source voltage ±25 V absolute maximum [datasheet p.1]; gate threshold VGS(th) -1.7 V min, -2.3 V typ, -2.8 V max at ID = -250 µA. [datasheet p.2]" }, { "number": "3", "name": "S1", "type": "passive",- "description": "Source of P-channel MOSFET #1. Connected to the source terminal of the first P-channel MOSFET die inside the dual package. [datasheet p.1]"+ "description": "Source of P-channel MOSFET 1 (S1), per the SOIC-8 top-view pinout and the internal schematic. [datasheet p.1]" }, { "number": "4", "name": "G1", "type": "input",- "description": "Gate of P-channel MOSFET #1. Gate threshold voltage VGS(th) = -1.7V to -2.8V (typical -2.3V). Maximum VGS = ±25V. [datasheet p.1]"+ "description": "Gate of P-channel MOSFET 1 (G1). Gate-source voltage ±25 V absolute maximum [datasheet p.1]; gate threshold VGS(th) -1.7 V min, -2.3 V typ, -2.8 V max at ID = -250 µA. [datasheet p.2]" }, { "number": "5", "name": "D1", "type": "passive",- "description": "Drain of P-channel MOSFET #1. Pins 5 and 6 are tied together internally for current handling and thermal performance. Drain-Source breakdown voltage BVDSS = -30V. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 1 (D1); pins 5 and 6 are both D1. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" }, { "number": "6", "name": "D1", "type": "passive",- "description": "Drain of P-channel MOSFET #1. Pins 5 and 6 are tied together internally for current handling and thermal performance. Drain-Source breakdown voltage BVDSS = -30V. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 1 (D1); pins 5 and 6 are both D1. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" }, { "number": "7", "name": "D2", "type": "passive",- "description": "Drain of P-channel MOSFET #2 (second drain lead). Pins 7 and 8 are tied together internally for current handling and thermal performance. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 2 (D2); pins 7 and 8 are both D2. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" }, { "number": "8", "name": "D2", "type": "passive",- "description": "Drain of P-channel MOSFET #2 (second drain lead). Pins 7 and 8 are tied together internally for current handling and thermal performance. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 2 (D2); pins 7 and 8 are both D2. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" } ], "provenance": {@@ -116,10 +115,12 @@ "at": "2026-10-09" }, "datasheet": {- "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175825766977536",+ "url": "https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf", "pages": 5,- "sha256": "d5ab4cd887b7c1672a7267d69cd345650440d5c5237104623195bbf4dfb5e148",- "source_tier": "lcsc"+ "sha256": "b7592fe0daec26e8e74483cf81c49e3ed593ddbe91949f2a1a70fd393e9c24bc",+ "source_tier": "mfr",+ "retrieved": "2026-10-27",+ "edition": "Rev 7.1, March 2024" }, "cad": "Footprint and symbol as used on Adom board designs; 3D model: KiCad library 3D model SOIC-8_3.9x4.9mm_P1.27mm (CC-BY-SA 4.0 with the KiCad library exception)", "pins": {@@ -129,10 +130,6 @@ "refuses_to_fabricate": true } },- "viewers": {- "symbol": "viewers/symbol.html",- "footprint": "viewers/footprint.html"- }, "models_3d": [ { "file": "ao4805.step",@@ -173,4 +170,4 @@ ] }, "description": "Alpha & Omega Semiconductor FET, MOSFET Arrays, SOIC-8. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet."-}+}
page.json+29−26@@ -4,14 +4,13 @@ "slug": "ao4805", "title": "AO4805", "brief": "Alpha & Omega Semiconductor FET, MOSFET Arrays, SOIC-8. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component", "transistors/thyristors", "ao4805",- "board-derived",- "staged-for-validation"+ "board-derived" ], "component": { "mpn": "AO4805",@@ -20,12 +19,12 @@ "pin_count": 8, "category": "Transistors/Thyristors", "subcategory": "FET, MOSFET Arrays",- "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175825766977536",+ "datasheet": "https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf", "parts": { "symbol": "ao4805.kicad_sym", "footprint": "ao4805.kicad_mod",- "model_3d": "ao4805-etched.glb",- "model_3d_plain": "ao4805.glb",+ "model_3d": "ao4805-hero.glb",+ "model_3d_plain": "ao4805-etched.glb", "model_3d_step": "ao4805-etched.step", "model_3d_step_plain": "ao4805.step", "lbr": "ao4805.lbr"@@ -36,7 +35,7 @@ "url": "https://www.digikey.com/en/products/detail/alpha-omega-semiconductor-inc/AO4805/1855827" }, "mouser": false,- "mouser_note": "2026-10-09: no exact-MPN listing for AO4805 found via the mouser API.",+ "mouser_note": "Not carried: searched AO4805 on 2026-10-09 and 2026-10-27 (Mouser returns no Alpha & Omega listing).", "lcsc": { "part": "C38943", "url": "https://www.lcsc.com/product-detail/C38943.html"@@ -47,49 +46,49 @@ "number": "1", "name": "S2", "type": "passive",- "description": "Source of P-channel MOSFET #2. Connected to the source terminal of the second P-channel MOSFET die inside the dual package. [datasheet p.1]"+ "description": "Source of P-channel MOSFET 2 (S2), per the SOIC-8 top-view pinout and the internal schematic. [datasheet p.1]" }, { "number": "2", "name": "G2", "type": "input",- "description": "Gate of P-channel MOSFET #2. Gate threshold voltage VGS(th) = -1.7V to -2.8V (typical -2.3V). Maximum VGS = ±25V. [datasheet p.1]"+ "description": "Gate of P-channel MOSFET 2 (G2). Gate-source voltage ±25 V absolute maximum [datasheet p.1]; gate threshold VGS(th) -1.7 V min, -2.3 V typ, -2.8 V max at ID = -250 µA. [datasheet p.2]" }, { "number": "3", "name": "S1", "type": "passive",- "description": "Source of P-channel MOSFET #1. Connected to the source terminal of the first P-channel MOSFET die inside the dual package. [datasheet p.1]"+ "description": "Source of P-channel MOSFET 1 (S1), per the SOIC-8 top-view pinout and the internal schematic. [datasheet p.1]" }, { "number": "4", "name": "G1", "type": "input",- "description": "Gate of P-channel MOSFET #1. Gate threshold voltage VGS(th) = -1.7V to -2.8V (typical -2.3V). Maximum VGS = ±25V. [datasheet p.1]"+ "description": "Gate of P-channel MOSFET 1 (G1). Gate-source voltage ±25 V absolute maximum [datasheet p.1]; gate threshold VGS(th) -1.7 V min, -2.3 V typ, -2.8 V max at ID = -250 µA. [datasheet p.2]" }, { "number": "5", "name": "D1", "type": "passive",- "description": "Drain of P-channel MOSFET #1. Pins 5 and 6 are tied together internally for current handling and thermal performance. Drain-Source breakdown voltage BVDSS = -30V. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 1 (D1); pins 5 and 6 are both D1. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" }, { "number": "6", "name": "D1", "type": "passive",- "description": "Drain of P-channel MOSFET #1. Pins 5 and 6 are tied together internally for current handling and thermal performance. Drain-Source breakdown voltage BVDSS = -30V. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 1 (D1); pins 5 and 6 are both D1. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" }, { "number": "7", "name": "D2", "type": "passive",- "description": "Drain of P-channel MOSFET #2 (second drain lead). Pins 7 and 8 are tied together internally for current handling and thermal performance. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 2 (D2); pins 7 and 8 are both D2. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" }, { "number": "8", "name": "D2", "type": "passive",- "description": "Drain of P-channel MOSFET #2 (second drain lead). Pins 7 and 8 are tied together internally for current handling and thermal performance. [datasheet p.1]"+ "description": "Drain of P-channel MOSFET 2 (D2); pins 7 and 8 are both D2. Drain-source voltage -30 V absolute maximum. [datasheet p.1]" } ], "provenance": {@@ -99,10 +98,12 @@ "at": "2026-10-09" }, "datasheet": {- "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175825766977536",+ "url": "https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf", "pages": 5,- "sha256": "d5ab4cd887b7c1672a7267d69cd345650440d5c5237104623195bbf4dfb5e148",- "source_tier": "lcsc"+ "sha256": "b7592fe0daec26e8e74483cf81c49e3ed593ddbe91949f2a1a70fd393e9c24bc",+ "source_tier": "mfr",+ "retrieved": "2026-10-27",+ "edition": "Rev 7.1, March 2024" }, "cad": "Footprint and symbol as used on Adom board designs; 3D model: KiCad library 3D model SOIC-8_3.9x4.9mm_P1.27mm (CC-BY-SA 4.0 with the KiCad library exception)", "pins": {@@ -121,11 +122,11 @@ "origin": "footprint origin", "seat": "z = 0 (PCB top surface)", "extents_mm": [- 6.0,+ 6, 4.9, 1.75 ],- "zmin_mm": -0.0,+ "zmin_mm": 0, "footprint_binding": "identity", "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a", "checked": "2026-10-09",@@ -139,11 +140,11 @@ "origin": "footprint origin", "seat": "z = 0 (PCB top surface)", "extents_mm": [- 6.0,+ 6, 4.9, 1.752 ],- "zmin_mm": -0.0,+ "zmin_mm": 0, "footprint_binding": "identity", "sha256": "aefb655bf896e27307480846a31ca84b872978362c86163dd9d3013cc935017a", "checked": "2026-10-09",@@ -194,9 +195,11 @@ "ao4805.step", "ao4805.lbr", "docs/hero.png",- "docs/ao4805-datasheet.pdf"+ "docs/ao4805-datasheet.pdf",+ "ao4805-hero.glb",+ "ao4805-hero.overlay.json" ],- "visibility": {- "public": false- }+ "visibility": "public",+ "description": "Alpha & Omega Semiconductor FET, MOSFET Arrays, SOIC-8. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.",+ "org": "adom" }
verification.json+68−1@@ -9,7 +9,7 @@ "name": "Claude (AI build)", "handle": "claude" },- "status": "open",+ "status": "superseded", "title": "Automated build checks (awaiting human validation)", "scope": [ "symbol",@@ -53,6 +53,73 @@ "ao4805.kicad_mod": "5be6a82529ce759fd0363b535bf4a2856612f5ef4a6007e670d74f5d8977a470", "ao4805.step": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a" }+ },+ {+ "date": "2026-10-27",+ "by": {+ "name": "Claude, at Caleb Taylor's request",+ "handle": "claude"+ },+ "status": "verified",+ "title": "Validated against Alpha & Omega's AO4805 datasheet (Rev 7.1, March 2024) and AOS SO8 package outline PO-00004 version L",+ "scope": [+ "symbol",+ "footprint",+ "3d",+ "pins"+ ],+ "variants": [+ "*"+ ],+ "checks": [+ {+ "text": "Datasheet: replaced the LCSC copy (2010 file) with AOS's current edition, Rev 7.1 March 2024, from aosmd.com (linked from the AO4805 product page; same file at aosmd.com/res/datasheets/AO4805.pdf). AOS lists the part as Full Production, package SO8",+ "result": "pass"+ },+ {+ "text": "All 8 pins match the SOIC-8 top-view pinout and internal schematic (p.1) by number and name: 1 S2, 2 G2, 3 S1, 4 G1, 5 D1, 6 D1, 7 D2, 8 D2. Die assignment checked: MOSFET 1 = G1 (4), S1 (3), D1 (5, 6); MOSFET 2 = G2 (2), S2 (1), D2 (7, 8). No renames needed",+ "result": "pass"+ },+ {+ "text": "Pin types: gates input, sources and drains passive (discrete MOSFET convention); unchanged",+ "result": "pass"+ },+ {+ "text": "Descriptions rewritten from the p.1 pinout, absolute maximum ratings (VDS -30 V, VGS ±25 V) and the p.2 VGS(th) row; every description cites the new PDF",+ "result": "pass"+ },+ {+ "text": "Footprint vs AOS SO8 outline PO-00004 L (no drawing in the datasheet itself): 8 pads 1.95 x 0.60 mm at e = 1.27 mm, pad centres 4.95 mm apart (pads span x 1.50 to 3.45 mm from centre) vs lead tips at E1/2 = 2.90-3.10 mm with foot L 0.40-1.27 mm, so the pads cover the feet; pad width 0.60 over b 0.31-0.51. AOS's recommended land pattern is larger (2.20 x 0.80 mm pads, centres 5.74 mm apart): the KiCad-library pads are smaller but still cover the leads. No exposed pad. Pin 1 top-left, numbering counter-clockwise",+ "result": "note"+ },+ {+ "text": "3D body (plain STEP) 6.00 x 4.90 x 1.75 mm against E1 5.80-6.20 (lead span), D 4.80-5.00, A 1.35-1.75; leads 0.41 mm wide on 1.27 mm pitch; pin-1 dot top-left over pad 1; Z-up, seated on z = 0, centred on the pads",+ "result": "pass"+ },+ {+ "text": "DigiKey 785-1055-2-ND confirmed as AO4805 by Alpha & Omega (tape and reel, Active); Mouser returned no Alpha & Omega listing for AO4805 (searched 2026-10-09 and 2026-10-27): set to not carried",+ "result": "pass"+ },+ {+ "text": "component-page-verify: all checks pass",+ "result": "pass"+ }+ ],+ "evidence": [+ {+ "label": "datasheet (Alpha & Omega, Rev 7.1)",+ "href": "https://www.aosmd.com/sites/default/files/res/datasheets/AO4805.pdf"+ },+ {+ "label": "SO8 package outline PO-00004 L (Alpha & Omega)",+ "href": "https://www.aosmd.com/sites/default/files/res/packaging_information/SO8.pdf"+ }+ ],+ "files": {+ "ao4805.kicad_sym": "32219c3c44615a4cfb818079a43ad7c86469616a280d0d76ad3c2d36a993b7b1",+ "ao4805.kicad_mod": "5be6a82529ce759fd0363b535bf4a2856612f5ef4a6007e670d74f5d8977a470",+ "ao4805.step": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a"+ } } ] }