AMT49413GEVATR

@@ -0,0 +1,90 @@+# AMT49413GEVATR++**Allegro MicroSystems LLC** · Brushless DC (BLDC) Motor Driver · QFN-48-EP(7x7)++AMT49413GEVATR from Allegro MicroSystems LLC, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | No internal connection. Leave floating or tie per application notes. |+| 2 | RESET | input | Reset / sleep-mode control input. Logic-level input rated -0.3 V to 6 V absolute max; drives the device into low-current sleep mode when asserted low. |+| 3 | V5BD | output | Internal 5 V regulator base drive. Connects to the external NPN pass-transistor base used with the on-chip 5 V regulator that powers the Hall sensors. |+| 4 | V5 | power_out | +5 V regulator reference / Hall sensor supply output. Decouple to AGND; also serves as the reference for the internal 5 V regulator. |+| 5 | FF2 | output | Fault flag output 2. Open-drain style diagnostic output; combined with FF1 to encode fault conditions (UVLO, TSD, short-to-supply, short-to-ground, shorted winding, low load). |+| 6 | FF1 | output | Fault flag output 1. Open-drain style diagnostic output; combined with FF2 to encode fault conditions. |+| 7 | TACHO | output | Tachometer / speed output. Digital pulse output indicating commutation events; usable as motor speed feedback. |+| 8 | BRAKE | input | Brake input. Logic-level input rated -0.3 V to 7 V absolute max; when asserted, forces a dynamic brake state on the outputs. |+| 9 | DIR | input | Direction control input. Logic-level input selecting motor rotation direction (forward/reverse). |+| 10 | H1 | input | Hall-effect sensor input 1. Digital input from the motor's Hall sensor for phase commutation decoding. |+| 11 | H2 | input | Hall-effect sensor input 2. Digital input from the motor's Hall sensor for phase commutation decoding. |+| 12 | H3 | input | Hall-effect sensor input 3. Digital input from the motor's Hall sensor for phase commutation decoding. |+| 13 | NC | unconnected | No internal connection. |+| 14 | PWM | input | PWM control input. Logic-level input used for speed/torque control; can chop the drive to set effective duty cycle while the internal current limit sets peak current. |+| 15 | MODE | input | Decay mode control input. Selects fast/slow current-decay mode for the internal PWM current regulator. |+| 16 | RC | passive | PWM oscillator RC timing pin. Connect an external RC (RT, CT) network to set the fixed PWM current-control frequency; tie directly to AGND to disable the internal PWM oscillator. |+| 17 | TEST | input | Factory test pin. Must be tied to AGND in normal operation. |+| 18 | RDEAD | passive | Dead-time setting pin. External resistor to AGND sets the cross-conduction / dead-time between high- and low-side gate transitions. |+| 19 | CSOUT | output | Current-sense amplifier output. Buffered analog output of the internal current-sense amplifier for monitoring load current. Rated -0.3 V to 6.5 V absolute max. |+| 20 | REF | input | Current-limit reference input. Analog reference voltage that, together with the external sense resistor, sets the peak load current limit. |+| 21 | CSN | input | Negative differential current-sense input. Connect across the external low-side sense resistor together with CSP. Rated -4 V to 6.5 V absolute max. |+| 22 | CSP | input | Positive differential current-sense input. Connect across the external low-side sense resistor together with CSN. Rated -4 V to 6.5 V absolute max. |+| 23 | VDSTH | input | VDS fault threshold voltage input. Analog input that sets the threshold used by the MOSFET VDS monitor for short-circuit / desat detection. Rated -0.3 V to 6.5 V absolute max. |+| 24 | VDRAIN | input | High-side MOSFET drain voltage sense input. Connect to the common drain node of the high-side FETs (motor supply); used for VDS monitoring and drain reference. Rated -0.3 V to 55 V absolute max. |+| 25 | SC | input | Motor phase-C connection / high-side source sense. Connect to the source of the phase-C high-side MOSFET (and drain of the low-side FET); reference for the phase-C bootstrap capacitor and floating high-side driver. Rated -5 V to 55 V absolute max. |+| 26 | GHC | output | High-side gate drive output, phase C. Drives the gate of the phase-C high-side N-channel MOSFET. Output range VSC to VSC+15 V. |+| 27 | CC | passive | Phase-C bootstrap capacitor pin. Connect a bootstrap capacitor between CC and SC to supply the floating high-side gate driver for phase C. Voltage range VSC + 15 V max. |+| 28 | SB | input | Motor phase-B connection / high-side source sense. Connect to the source of the phase-B high-side MOSFET (and drain of the low-side FET); reference for the phase-B bootstrap capacitor. Rated -5 V to 55 V absolute max. |+| 29 | GHB | output | High-side gate drive output, phase B. Drives the gate of the phase-B high-side N-channel MOSFET. Output range VSB to VSB+15 V. |+| 30 | CB | passive | Phase-B bootstrap capacitor pin. Connect a bootstrap capacitor between CB and SB to supply the floating high-side gate driver for phase B. |+| 31 | SA | input | Motor phase-A connection / high-side source sense. Connect to the source of the phase-A high-side MOSFET (and drain of the low-side FET); reference for the phase-A bootstrap capacitor. Rated -5 V to 55 V absolute max. |+| 32 | GHA | output | High-side gate drive output, phase A. Drives the gate of the phase-A high-side N-channel MOSFET. Output range VSA to VSA+15 V. |+| 33 | CA | passive | Phase-A bootstrap capacitor pin. Connect a bootstrap capacitor between CA and SA to supply the floating high-side gate driver for phase A. |+| 34 | GLC | output | Low-side gate drive output, phase C. Drives the gate of the phase-C low-side N-channel MOSFET, referenced to LSS. Rated -5 V to 16 V absolute max. |+| 35 | GLB | output | Low-side gate drive output, phase B. Drives the gate of the phase-B low-side N-channel MOSFET, referenced to LSS. Rated -5 V to 16 V absolute max. |+| 36 | GLA | output | Low-side gate drive output, phase A. Drives the gate of the phase-A low-side N-channel MOSFET, referenced to LSS. Rated -5 V to 16 V absolute max. |+| 37 | NC | unconnected | No internal connection. |+| 38 | LSS | power_in | Low-side MOSFET source / common return. Connect to the common source of the low-side power MOSFETs and to the top of the external current-sense resistor; reference for the low-side gate drivers. Rated -4 V to 6.5 V absolute max. |+| 39 | ESF | input | Enable-stop-on-fault input. Logic-level input; when enabled, causes the driver to disable outputs on latched fault conditions. |+| 40 | VREG | power_out | Internal gate-drive regulator output. Regulated supply for the low-side gate drivers and bootstrap top-up; decouple to AGND with a ceramic capacitor. |+| 41 | AGND | power_in | Analog ground. Reference for the analog circuitry, timing network, and current-sense amplifier; connect to the exposed thermal pad and to system ground per PCB guidance. |+| 42 | CP1 | passive | Charge-pump flying capacitor terminal 1. Connect an external ceramic capacitor between CP1 and CP2 for the on-chip charge-pump regulator (provides >10 V gate drive down to 7 V VBB). |+| 43 | CP2 | passive | Charge-pump flying capacitor terminal 2. Connect the external charge-pump capacitor between CP1 and CP2. |+| 44 | DIRO | output | Direction indicator output. Logic-level output reporting the currently selected motor rotation direction. |+| 45 | VBB | power_in | Load / battery supply voltage input. Main power supply pin; operating range 5.5 V to 50 V (absolute max -0.3 V to 50 V). Decouple with bulk and local ceramic capacitors. |+| 46 | COAST | input | Coast input. Logic-level input; when asserted, disables all gate drives so the motor coasts (all FETs off). |+| 47 | NC | unconnected | No internal connection. |+| 48 | NC | unconnected | No internal connection. |+| 49 | PAD | power_in | Exposed thermal pad on package underside. Tie to AGND and to a copper ground plane with thermal vias for heat dissipation; RθJP = 2 °C/W. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Allegro MicroSystems LLC |+| Package | QFN-48-EP(7x7) |+| Category | Motor Driver ICs |+| Pins | 49 |++## Ordering variants++Same part, different packaging or reel option.++- `AMT49413GEVATR`++## CAD (KiCad official)++- Symbol: `AMT49413GEVATR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893370328080384) (None pp, sha256 `8ce78a6c34f09a58`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/amt49413gevatr-datasheet.pdf)