component
AM3505AZER
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), BGA-484. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+520@@ -0,0 +1,520 @@+# AM3505AZER++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · BGA-484++AM3505AZER from Texas Instruments, in a BGA-484. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| E3 | sdrc_d0 | bidirectional | SDRC data bit 0 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| D3 | sdrc_d1 | bidirectional | SDRC data bit 1 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| C3 | sdrc_d2 | bidirectional | SDRC data bit 2 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| C2 | sdrc_d3 | bidirectional | SDRC data bit 3 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| F3 | sdrc_d4 | bidirectional | SDRC data bit 4 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| D2 | sdrc_d5 | bidirectional | SDRC data bit 5 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| C1 | sdrc_d6 | bidirectional | SDRC data bit 6 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| D1 | sdrc_d7 | bidirectional | SDRC data bit 7 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| G2 | sdrc_d8 | bidirectional | SDRC data bit 8 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| G3 | sdrc_d9 | bidirectional | SDRC data bit 9 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| H3 | sdrc_d10 | bidirectional | SDRC data bit 10 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| G4 | sdrc_d11 | bidirectional | SDRC data bit 11 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| H4 | sdrc_d12 | bidirectional | SDRC data bit 12 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| G1 | sdrc_d13 | bidirectional | SDRC data bit 13 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| J3 | sdrc_d14 | bidirectional | SDRC data bit 14 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| J1 | sdrc_d15 | bidirectional | SDRC data bit 15 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| T3 | sdrc_d16 | bidirectional | SDRC data bit 16 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| U3 | sdrc_d17 | bidirectional | SDRC data bit 17 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| U4 | sdrc_d18 | bidirectional | SDRC data bit 18 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| V4 | sdrc_d19 | bidirectional | SDRC data bit 19 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| V1 | sdrc_d20 | bidirectional | SDRC data bit 20 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| V2 | sdrc_d21 | bidirectional | SDRC data bit 21 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| V5 | sdrc_d22 | bidirectional | SDRC data bit 22 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| V3 | sdrc_d23 | bidirectional | SDRC data bit 23 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| W3 | sdrc_d24 | bidirectional | SDRC data bit 24 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| W4 | sdrc_d25 | bidirectional | SDRC data bit 25 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| Y3 | sdrc_d26 | bidirectional | SDRC data bit 26 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| Y4 | sdrc_d27 | bidirectional | SDRC data bit 27 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| AA2 | sdrc_d28 | bidirectional | SDRC data bit 28 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| AA3 | sdrc_d29 | bidirectional | SDRC data bit 29 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| AA4 | sdrc_d30 | bidirectional | SDRC data bit 30 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| AB2 | sdrc_d31 | bidirectional | SDRC data bit 31 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD. |+| L4 | sdrc_ba0 | output | SDRC bank address bit 0 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| K5 | sdrc_ba1 | output | SDRC bank address bit 1 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| J5 | sdrc_ba2 | output | SDRC bank address bit 2 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| M3 | sdrc_a0 | output | SDRC address bit 0 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| M4 | sdrc_a1 | output | SDRC address bit 1 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| M5 | sdrc_a2 | output | SDRC address bit 2 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| N3 | sdrc_a3 | output | SDRC address bit 3 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| N2 | sdrc_a4 | output | SDRC address bit 4 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| N4 | sdrc_a5 | output | SDRC address bit 5 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| P3 | sdrc_a6 | output | SDRC address bit 6 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| P2 | sdrc_a7 | output | SDRC address bit 7 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| P1 | sdrc_a8 | output | SDRC address bit 8 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| P4 | sdrc_a9 | output | SDRC address bit 9 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| R1 | sdrc_a10 | output | SDRC address bit 10 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| R2 | sdrc_a11 | output | SDRC address bit 11 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| R3 | sdrc_a12 | output | SDRC address bit 12 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| R4 | sdrc_a13 | output | SDRC address bit 13 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| T2 | sdrc_a14 | output | SDRC address bit 14 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| J4 | sdrc_ncs0 | output | SDRC chip select 0 (active low) output on VDDS (1.8 V), 8 pF load, reset state Z. |+| K4 | sdrc_ncs1 | output | SDRC chip select 1 (active low) output on VDDS (1.8 V), 8 pF load, reset state Z. |+| L1 | sdrc_clk | output | SDRC differential clock output (true) on VDDS (1.8 V), 8 pF load, reset state Z. |+| L2 | sdrc_nclk | output | SDRC differential clock output (complement) on VDDS (1.8 V), 8 pF load, reset state Z. |+| K3 | sdrc_cke0 | output | SDRC clock enable 0 on VDDS (1.8 V), 8 pF load, reset state 0 with pulldown; mode 7 provides sdrc_cke0_safe. |+| K1 | sdrc_nras | output | SDRC row address strobe output on VDDS (1.8 V), 8 pF load, reset state Z. |+| L3 | sdrc_ncas | output | SDRC column address strobe output on VDDS (1.8 V), 8 pF load, reset state Z. |+| K2 | sdrc_nwe | output | SDRC write enable output on VDDS (1.8 V), 8 pF load, reset state Z. |+| F4 | sdrc_dm0 | output | SDRC data mask 0 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| J2 | sdrc_dm1 | output | SDRC data mask 1 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| T4 | sdrc_dm2 | output | SDRC data mask 2 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| AB3 | sdrc_dm3 | output | SDRC data mask 3 output on VDDS (1.8 V), 8 pF load, reset state Z. |+| E2 | sdrc_dqs0p | bidirectional | SDRC data strobe 0 true on VDDS (1.8 V), reset state Z, hysteresis enabled. |+| H2 | sdrc_dqs1p | bidirectional | SDRC data strobe 1 true on VDDS (1.8 V), reset state Z, hysteresis enabled. |+| U1 | sdrc_dqs2p | bidirectional | SDRC data strobe 2 true on VDDS (1.8 V), reset state Z, hysteresis enabled. |+| Y1 | sdrc_dqs3p | bidirectional | SDRC data strobe 3 true on VDDS (1.8 V), reset state Z, hysteresis enabled. |+| E1 | sdrc_dqs0n | bidirectional | SDRC data strobe 0 complement on VDDS (1.8 V), reset state Z. |+| H1 | sdrc_dqs1n | bidirectional | SDRC data strobe 1 complement on VDDS (1.8 V), reset state Z. |+| U2 | sdrc_dqs2n | bidirectional | SDRC data strobe 2 complement on VDDS (1.8 V), reset state Z. |+| Y2 | sdrc_dqs3n | bidirectional | SDRC data strobe 3 complement on VDDS (1.8 V), reset state Z. |+| T1 | sdrc_odt | output | SDRC on-die termination control on VDDS (1.8 V), 8 pF load, reset state Z. |+| F2 | sdrc_strben0 | output | SDRC read strobe enable 0 on VDDS (1.8 V), 8 pF load, reset state Z. |+| F1 | sdrc_strben_dly0 | output | SDRC read strobe enable delayed 0 on VDDS (1.8 V), 8 pF load, reset state Z. |+| W1 | sdrc_strben1 | output | SDRC read strobe enable 1 on VDDS (1.8 V), 8 pF load, reset state Z. |+| W2 | sdrc_strben_dly1 | output | SDRC read strobe enable delayed 1 on VDDS (1.8 V), 8 pF load, reset state Z. |+| W5 | gpmc_a1 | output | GPMC address bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| Y5 | gpmc_a2 | output | GPMC address bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| AB4 | gpmc_a3 | output | GPMC address bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| AA5 | gpmc_a4 | output | GPMC address bit 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| AB5 | gpmc_a5 | output | GPMC address bit 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| AB6 | gpmc_a6 | output | GPMC address bit 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| AA6 | gpmc_a7 | output | GPMC address bit 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| W6 | gpmc_a8 | output | GPMC address bit 8 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| AB7 | gpmc_a9 | output | GPMC address bit 9 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq2 in mode 1. |+| Y6 | gpmc_a10 | output | GPMC address bit 10 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq3 in mode 1. |+| AA7 | gpmc_d0 | bidirectional | GPMC data bit 0 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, internal PU/PD. |+| Y7 | gpmc_d1 | bidirectional | GPMC data bit 1 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| W7 | gpmc_d2 | bidirectional | GPMC data bit 2 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| AA9 | gpmc_d3 | bidirectional | GPMC data bit 3 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| Y8 | gpmc_d4 | bidirectional | GPMC data bit 4 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| AA8 | gpmc_d5 | bidirectional | GPMC data bit 5 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| AB8 | gpmc_d6 | bidirectional | GPMC data bit 6 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| W8 | gpmc_d7 | bidirectional | GPMC data bit 7 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| W10 | gpmc_d8 | bidirectional | GPMC data bit 8 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_44 in mode 4. |+| AB9 | gpmc_d9 | bidirectional | GPMC data bit 9 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_45 in mode 4. |+| AB10 | gpmc_d10 | bidirectional | GPMC data bit 10 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_46 in mode 4. |+| W9 | gpmc_d11 | bidirectional | GPMC data bit 11 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_47 in mode 4. |+| AA10 | gpmc_d12 | bidirectional | GPMC data bit 12 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_48 in mode 4. |+| Y9 | gpmc_d13 | bidirectional | GPMC data bit 13 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_49 in mode 4. |+| V10 | gpmc_d14 | bidirectional | GPMC data bit 14 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_50 in mode 4. |+| V9 | gpmc_d15 | bidirectional | GPMC data bit 15 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_51 in mode 4. |+| Y10 | gpmc_ncs0 | output | GPMC chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance, no pull. |+| Y11 | gpmc_ncs1 | output | GPMC chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance; also gpio_52 in mode 4. |+| Y12 | gpmc_ncs2 | output | GPMC chip select 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpt9_pwm_evt and gpio_53. |+| V12 | gpmc_ncs3 | output | GPMC chip select 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq0, gpt10_pwm_evt, gpio_54. |+| AA11 | gpmc_ncs4 | output | GPMC chip select 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq1, gpt9_pwm_evt, gpio_55. |+| W12 | gpmc_ncs5 | output | GPMC chip select 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq2, gpt10_pwm_evt, gpio_56. |+| AA12 | gpmc_ncs6 | output | GPMC chip select 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq3, gpt11_pwm_evt, gpio_57. |+| V11 | gpmc_ncs7 | output | GPMC chip select 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpmc_io_dir, gpt8_pwm_evt, gpio_58. |+| AB13 | gpmc_clk | output | GPMC clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_59. |+| AA14 | gpmc_nadv_ale | output | GPMC address valid / address latch enable on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance. |+| AB14 | gpmc_noe | output | GPMC output enable (active low) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance. |+| AA15 | gpmc_nwe | output | GPMC write enable (active low) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance. |+| W11 | gpmc_nbe0_cle | output | GPMC byte enable 0 / command latch enable on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_60. |+| Y15 | gpmc_nbe1 | output | GPMC byte enable 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpio_61. |+| W14 | gpmc_nwp | output | GPMC write protect on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_62. |+| V13 | gpmc_wait0 | input | GPMC wait input 0 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled. |+| AA16 | gpmc_wait1 | input | GPMC wait input 1 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also uart4_tx and gpio_63. |+| Y14 | gpmc_wait2 | input | GPMC wait input 2 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also uart4_rx and gpio_64. |+| V14 | gpmc_wait3 | input | GPMC wait input 3 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also sys_ndmareq1, uart3_ctsn and gpio_65. |+| B22 | dss_pclk | output | Display subsystem pixel clock on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup. |+| B21 | dss_hsync | output | Display subsystem horizontal sync on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup. |+| B20 | dss_vsync | output | Display subsystem vertical sync on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup. |+| B19 | dss_acbias | output | Display subsystem AC bias output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| A20 | dss_data0 | output | Display subsystem data bit 0 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_cts. |+| A19 | dss_data1 | output | Display subsystem data bit 1 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_rts. |+| A18 | dss_data2 | output | Display subsystem data bit 2 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| B18 | dss_data3 | output | Display subsystem data bit 3 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| A17 | dss_data4 | output | Display subsystem data bit 4 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart3_rx_irrx. |+| C18 | dss_data5 | output | Display subsystem data bit 5 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart3_tx_irtx. |+| D17 | dss_data6 | output | Display subsystem data bit 6 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_tx. |+| B16 | dss_data7 | output | Display subsystem data bit 7 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_rx. |+| B17 | dss_data8 | output | Display subsystem data bit 8 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| C17 | dss_data9 | output | Display subsystem data bit 9 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| C16 | dss_data10 | output | Display subsystem data bit 10 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| D16 | dss_data11 | output | Display subsystem data bit 11 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| D14 | dss_data12 | output | Display subsystem data bit 12 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| A16 | dss_data13 | output | Display subsystem data bit 13 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| D15 | dss_data14 | output | Display subsystem data bit 14 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| B15 | dss_data15 | output | Display subsystem data bit 15 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| A15 | dss_data16 | output | Display subsystem data bit 16 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| A14 | dss_data17 | output | Display subsystem data bit 17 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| C13 | dss_data18 | output | Display subsystem data bit 18 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_clk. |+| C15 | dss_data19 | output | Display subsystem data bit 19 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_simo. |+| A13 | dss_data20 | output | Display subsystem data bit 20 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_somi. |+| B13 | dss_data21 | output | Display subsystem data bit 21 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_cs0. |+| C14 | dss_data22 | output | Display subsystem data bit 22 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_cs1. |+| B14 | dss_data23 | output | Display subsystem data bit 23 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| AB21 | ccdc_pclk | bidirectional | CCDC pixel clock on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg0 and gpio_94. |+| AA21 | ccdc_field | bidirectional | CCDC field signal on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also ccdc_data8, uart4_tx and i2c3_scl. |+| Y21 | ccdc_hd | bidirectional | CCDC horizontal sync on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also uart4_rts. |+| Y22 | ccdc_vd | bidirectional | CCDC vertical sync on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also uart4_cts. |+| W21 | ccdc_wen | bidirectional | CCDC write enable on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also ccdc_data9 and uart4_rx. |+| W22 | ccdc_data0 | input | CCDC data bit 0 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also i2c3_sda. |+| W20 | ccdc_data1 | input | CCDC data bit 1 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown. |+| V21 | ccdc_data2 | input | CCDC data bit 2 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg4. |+| V19 | ccdc_data3 | input | CCDC data bit 3 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg5. |+| V22 | ccdc_data4 | input | CCDC data bit 4 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg6. |+| U20 | ccdc_data5 | input | CCDC data bit 5 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg7. |+| V20 | ccdc_data6 | input | CCDC data bit 6 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown. |+| U19 | ccdc_data7 | input | CCDC data bit 7 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown. |+| U21 | rmii_mdio_data | bidirectional | EMAC RMII management data on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data8 and gpio_107. |+| U22 | rmii_mdio_clk | output | EMAC RMII management clock on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data9 and gpio_108. |+| T19 | rmii_rxd0 | input | EMAC RMII receive data bit 0 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data10. |+| T20 | rmii_rxd1 | input | EMAC RMII receive data bit 1 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data11. |+| T21 | rmii_crs_dv | input | EMAC RMII carrier sense / receive data valid on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup. |+| R22 | rmii_rxer | input | EMAC RMII receive error on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data13. |+| T22 | rmii_txd0 | output | EMAC RMII transmit data bit 0 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup. |+| R20 | rmii_txd1 | output | EMAC RMII transmit data bit 1 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup. |+| R19 | rmii_txen | output | EMAC RMII transmit enable on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup. |+| R21 | rmii_50mhz_clk | input | EMAC RMII 50 MHz reference clock input on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup. |+| E5 | mcbsp2_fsx | bidirectional | McBSP2 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| D5 | mcbsp2_clkx | bidirectional | McBSP2 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| C5 | mcbsp2_dr | input | McBSP2 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| E4 | mcbsp2_dx | bidirectional | McBSP2 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| P22 | mmc1_clk | output | MMC1 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| N21 | mmc1_cmd | bidirectional | MMC1 command on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| P21 | mmc1_dat0 | bidirectional | MMC1 data bit 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_clk. |+| N20 | mmc1_dat1 | bidirectional | MMC1 data bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_simo. |+| P19 | mmc1_dat2 | bidirectional | MMC1 data bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_somi. |+| P20 | mmc1_dat3 | bidirectional | MMC1 data bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_cs0. |+| N22 | mmc1_dat4 | bidirectional | MMC1 data bit 4 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_126. |+| N19 | mmc1_dat5 | bidirectional | MMC1 data bit 5 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_127. |+| N18 | mmc1_dat6 | bidirectional | MMC1 data bit 6 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_128. |+| P18 | mmc1_dat7 | bidirectional | MMC1 data bit 7 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_129. |+| M21 | mmc2_clk | output | MMC2 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi3_clk, uart4_cts. |+| M20 | mmc2_cmd | bidirectional | MMC2 command on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_simo and uart4_rts. |+| K20 | mmc2_dat0 | bidirectional | MMC2 data bit 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_somi and uart4_tx. |+| L19 | mmc2_dat1 | bidirectional | MMC2 data bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also uart4_rx. |+| M18 | mmc2_dat2 | bidirectional | MMC2 data bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_cs1. |+| K21 | mmc2_dat3 | bidirectional | MMC2 data bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_cs0. |+| L18 | mmc2_dat4 | bidirectional | MMC2 data bit 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_data0 and mmc3_dat0. |+| L20 | mmc2_dat5 | bidirectional | MMC2 data bit 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_data1 and mmc3_dat1. |+| L21 | mmc2_dat6 | bidirectional | MMC2 data bit 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_cmd and mmc3_dat2. |+| M19 | mmc2_dat7 | bidirectional | MMC2 data bit 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_clkin and mmc3_dat3. |+| C4 | mcbsp3_dx | bidirectional | McBSP3 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_cts. |+| B4 | mcbsp3_dr | input | McBSP3 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_rts. |+| D4 | mcbsp3_clkx | bidirectional | McBSP3 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_tx. |+| A4 | mcbsp3_fsx | bidirectional | McBSP3 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_rx. |+| A5 | uart2_cts | input | UART2 clear to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| B5 | uart2_rts | output | UART2 request to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| D6 | uart2_tx | output | UART2 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| C6 | uart2_rx | input | UART2 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| C22 | uart1_tx | output | UART1 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| C21 | uart1_rts | output | UART1 request to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| C19 | uart1_cts | input | UART1 clear to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| C20 | uart1_rx | input | UART1 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcbsp1_clkr and mcspi4_clk. |+| A3 | mcbsp4_clkx | bidirectional | McBSP4 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txse0. |+| B3 | mcbsp4_dr | input | McBSP4 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_rxrcv. |+| A2 | mcbsp4_dx | bidirectional | McBSP4 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txdat. |+| B2 | mcbsp4_fsx | bidirectional | McBSP4 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txen_n. |+| B11 | mcbsp1_clkr | bidirectional | McBSP1 receive clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_clk. |+| D11 | mcbsp1_fsr | bidirectional | McBSP1 frame sync receive on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown. |+| C10 | mcbsp1_dx | bidirectional | McBSP1 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_simo and mcbsp3_dx. |+| C9 | mcbsp1_dr | input | McBSP1 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_somi and mcbsp3_dr. |+| E11 | mcbsp_clks | input | McBSP sample rate clock input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart1_cts. |+| C11 | mcbsp1_fsx | bidirectional | McBSP1 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_cs0 and mcbsp3_fsx. |+| C8 | mcbsp1_clkx | bidirectional | McBSP1 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcbsp3_clkx. |+| W15 | uart3_cts_rctx | bidirectional | UART3 clear to send (input) / remote TX (output) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| W13 | uart3_rts_sd | output | UART3 request to send / IR enable output on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| AA13 | uart3_rx_irrx | input | UART3 receive data / IR and remote RX input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| Y13 | uart3_tx_irtx | output | UART3 transmit data / IR TX output on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup. |+| A6 | usb0_dp | bidirectional | USB0 D+ differential signal pair, 5.0 V tolerant, with internal PU/PD. |+| B6 | usb0_dm | bidirectional | USB0 D- differential signal pair, 5.0 V tolerant, with internal PU/PD. |+| C7 | usb0_vbus | passive | USB0 VBUS analog input; tie to USB connector (host/device) or external charge pump and VBUS (OTG), VDDA3P3V_USBPHY 3.3 V. |+| B7 | usb0_id | passive | USB0 operating mode identification (analog) pin on VDDA3P3V_USBPHY (3.3 V). |+| A7 | usb0_drvvbus | output | Digital output controlling external VBUS supply on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart3_tx_irtx and gpio_125. |+| AB15 | hecc1_txd | output | HECC1 CAN transmit on VDDSHV (1.8 V/3.3 V), 24 pF load, reset state 1 with pullup; also uart3_rx_irrx and gpio_130. |+| AB16 | hecc1_rxd | input | HECC1 CAN receive on VDDSHV (1.8 V/3.3 V), 24 pF load, reset state 1 with pullup; also uart3_rts_sd and gpio_131. |+| AA17 | i2c1_scl | bidirectional | I2C1 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup. |+| AB17 | i2c1_sda | bidirectional | I2C1 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup. |+| Y17 | i2c2_scl | bidirectional | I2C2 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_168. |+| Y16 | i2c2_sda | bidirectional | I2C2 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_183. |+| W16 | i2c3_scl | bidirectional | I2C3 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_184. |+| W17 | i2c3_sda | bidirectional | I2C3 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_185. |+| B9 | hdq_sio | bidirectional | HDQ/1-Wire single-wire data on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup. |+| K22 | mcspi1_clk | bidirectional | McSPI1 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat4. |+| K19 | mcspi1_simo | bidirectional | McSPI1 SIMO on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat5. |+| J18 | mcspi1_somi | bidirectional | McSPI1 SOMI on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat6. |+| K18 | mcspi1_cs0 | bidirectional | McSPI1 chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc2_dat7. |+| J20 | mcspi1_cs1 | output | McSPI1 chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc3_cmd. |+| J19 | mcspi1_cs2 | output | McSPI1 chip select 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc3_clk. |+| J21 | mcspi1_cs3 | output | McSPI1 chip select 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also hsusb2_data2 and mm_fsusb2_txdat. |+| J22 | mcspi2_clk | bidirectional | McSPI2 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also hsusb2_data7. |+| H20 | mcspi2_simo | bidirectional | McSPI2 SIMO on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt9_pwm_evt and hsusb2_data4. |+| H22 | mcspi2_somi | bidirectional | McSPI2 SOMI on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt10_pwm_evt and hsusb2_data5. |+| H21 | mcspi2_cs0 | bidirectional | McSPI2 chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpt11_pwm_evt and hsusb2_data6. |+| H19 | mcspi2_cs1 | output | McSPI2 chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt8_pwm_evt and hsusb2_data3. |+| A8 | sys_32k | input | 32 kHz clock input on VDDSHV (1.8 V/3.3 V), 30 pF load, high-impedance at reset. |+| A10 | sys_xtalin | input | Oscillator crystal input on VDDSOSC (1.8 V), high-impedance at reset. |+| A9 | sys_xtalout | output | Oscillator crystal output on VDDSOSC (1.8 V), high-impedance at reset. |+| B8 | sys_clkreq | bidirectional | System clock request on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_1. |+| AB18 | sys_nirq | input | System interrupt input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpio_0. |+| AA18 | sys_nrespwron | input | Power-on reset input on VDDSHV (1.8 V/3.3 V), high-impedance at reset. |+| Y18 | sys_nreswarm | bidirectional | Warm reset bidirectional on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; open-drain function on gpio_30. |+| AB19 | sys_boot0 | input | Boot configuration input 0 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_2. |+| AB20 | sys_boot1 | input | Boot configuration input 1 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_3. |+| W18 | sys_boot2 | input | Boot configuration input 2 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_4. |+| AA19 | sys_boot3 | input | Boot configuration input 3 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_5. |+| V18 | sys_boot4 | input | Boot configuration input 4 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also mmc2_dir_data2 and gpio_6. |+| Y19 | sys_boot5 | input | Boot configuration input 5 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also mmc2_dir_data3 and gpio_7. |+| W19 | sys_boot6 | input | Boot configuration input 6 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_8. |+| AA20 | sys_boot7 | input | Boot configuration input 7 on VDDSHV (1.8 V/3.3 V), high-impedance at reset with pullup. |+| Y20 | sys_boot8 | input | Boot configuration input 8 on VDDSHV (1.8 V/3.3 V), high-impedance at reset with pullup. |+| E9 | sys_clkout1 | output | System clock output 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pulldown; mux 0 if sys_boot6 is pulled down (clock master); also gpio_10. |+| E10 | sys_clkout2 | output | System clock output 2 on VDDSHV (1.8 V/3.3 V), 10 pF load, reset state 0 with pulldown; also gpio_186. |+| D13 | jtag_ntrst | input | JTAG test reset input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| E14 | jtag_tck | input | JTAG test clock input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown. |+| C12 | jtag_rtck | output | JTAG return test clock output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 high-impedance. |+| A12 | jtag_tms_tmsc | bidirectional | JTAG test mode select / TMSC on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup. |+| B12 | jtag_tdi | input | JTAG test data input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup. |+| D12 | jtag_tdo | output | JTAG test data output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 high-impedance. |+| E13 | jtag_emu0 | bidirectional | JTAG emulation pin 0 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup; also gpio_11. |+| E12 | jtag_emu1 | bidirectional | JTAG emulation pin 1 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup; also gpio_31. |+| G22 | etk_clk | output | ETK trace clock on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcbsp5_clkx, mmc3_clk, hsusb1_stp and gpio_12. |+| G21 | etk_ctl | output | ETK trace control on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mmc3_cmd, hsusb1_clk and gpio_13. |+| G20 | etk_d0 | output | ETK trace data bit 0 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_simo and hsusb1_data0. |+| F22 | etk_d1 | output | ETK trace data bit 1 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_somi and hsusb1_data1. |+| F20 | etk_d2 | output | ETK trace data bit 2 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_cs0 and hsusb1_data2. |+| G19 | etk_d3 | output | ETK trace data bit 3 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pullup; also mcspi3_clk and hsusb1_data7. |+| E19 | etk_d4 | output | ETK trace data bit 4 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_dr and hsusb1_data4. |+| F21 | etk_d5 | output | ETK trace data bit 5 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_fsx and hsusb1_data5. |+| F19 | etk_d6 | output | ETK trace data bit 6 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_dx and hsusb1_data6. |+| E21 | etk_d7 | output | ETK trace data bit 7 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcspi3_cs1 and hsusb1_data3. |+| D22 | etk_d8 | output | ETK trace data bit 8 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mmc3_dat6 and hsusb1_dir. |+| D21 | etk_d9 | output | ETK trace data bit 9 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mmc3_dat5 and hsusb1_nxt. |+| E22 | etk_d10 | output | ETK trace data bit 10 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also uart1_rx and hsusb2_clk. |+| E20 | etk_d11 | output | ETK trace data bit 11 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcspi3_clk and hsusb2_stp. |+| E18 | etk_d12 | output | ETK trace data bit 12 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_dir. |+| D20 | etk_d13 | output | ETK trace data bit 13 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_nxt. |+| D19 | etk_d14 | output | ETK trace data bit 14 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_data0. |+| D18 | etk_d15 | output | ETK trace data bit 15 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_data1. |+| M2 | ddr_padref | passive | DDR pad reference voltage on VDDS (1.8 V). |+| J8 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| J10 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| J12 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| J14 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| J16 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| K9 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| K11 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| K13 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| K15 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| L8 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| L10 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| L12 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| L14 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| M7 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| M9 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| M11 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| M13 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| M15 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| N8 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| N10 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| N12 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| N14 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| P7 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| P9 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| P11 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| P13 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| P15 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| R8 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| R10 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| R12 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| R14 | VDD_CORE | power_in | Core logic supply, 1.2 V nominal. |+| L17 | VDDS_SRAM_MPU | power_in | SRAM supply for the MPU domain, 1.8 V. |+| J6 | VDDS_SRAM_CORE_BG | power_in | SRAM supply for the core domain (bandgap), 1.8 V. |+| M17 | CAP_VDD_SRAM_MPU | power_in | SRAM core voltage capacitor node for the MPU domain, 1.2 V. |+| K6 | CAP_VDD_SRAM_CORE | power_in | SRAM core voltage capacitor node for the core domain, 1.2 V. |+| K17 | VDDS_DPLL_MPU_USBHOST | power_in | DPLL supply for MPU and USB host clocks, 1.8 V; requires the noise filter in Table 5-19. |+| F11 | VDDS_DPLL_PER_CORE | power_in | DPLL supply for peripheral and core clocks, 1.8 V; requires the noise filter in Table 5-19. |+| F7 | VDDA3P3V_USBPHY | power_in | USB PHY analog supply, 3.3 V. |+| D7 | VDDA1P8V_USBPHY | power_in | USB PHY analog supply, 1.8 V. |+| E7 | CAP_VDDA1_P2LDO_USBPHY | passive | USB PHY internal LDO capacitor node, 1.2 V (printed name wraps across lines). |+| A21 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| B1 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| E15 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| E17 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| F12 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| F14 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| F18 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| G10 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| G12 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| G13 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| G8 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| G17 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| H18 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| J17 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| L22 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| N16 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| P17 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| R16 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| R18 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| T9 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| T11 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| T13 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| T17 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| U8 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| U10 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| U12 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| U14 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| U16 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| U18 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| V7 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| V8 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| V17 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| AA22 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| AB11 | VDDSHV | power_in | I/O supply for 1.8 V/3.3 V peripheral buffers. |+| F5 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| F16 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| G15 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| H5 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| K7 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| L6 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| L16 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| N1 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| N5 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| N6 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| P5 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| R6 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| T5 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| T7 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| T15 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| U6 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| AA1 | VDDS | power_in | I/O supply for DDR2/mDDR interface buffers, 1.8 V. |+| L5 | VREFSSTL | input | DDR SSTL reference voltage input, 0.5 × VDDS. |+| G9 | VDDSOSC | power_in | Oscillator supply, 1.8 V. |+| B10 | VSSOSC | power_in | Oscillator ground. |+| A1 | VSS | power_in | Ground. |+| A11 | VSS | power_in | Ground. |+| A22 | VSS | power_in | Ground. |+| E6 | VSS | power_in | Ground. |+| E16 | VSS | power_in | Ground. |+| F6 | VSS | power_in | Ground. |+| F13 | VSS | power_in | Ground. |+| F15 | VSS | power_in | Ground. |+| F17 | VSS | power_in | Ground. |+| G5 | VSS | power_in | Ground. |+| G7 | VSS | power_in | Ground. |+| G11 | VSS | power_in | Ground. |+| G14 | VSS | power_in | Ground. |+| G16 | VSS | power_in | Ground. |+| G18 | VSS | power_in | Ground. |+| H6 | VSS | power_in | Ground. |+| H7 | VSS | power_in | Ground. |+| H8 | VSS | power_in | Ground. |+| H9 | VSS | power_in | Ground. |+| H10 | VSS | power_in | Ground. |+| H11 | VSS | power_in | Ground. |+| H12 | VSS | power_in | Ground. |+| H13 | VSS | power_in | Ground. |+| H14 | VSS | power_in | Ground. |+| H15 | VSS | power_in | Ground. |+| H16 | VSS | power_in | Ground. |+| H17 | VSS | power_in | Ground. |+| J9 | VSS | power_in | Ground. |+| J11 | VSS | power_in | Ground. |+| J13 | VSS | power_in | Ground. |+| J15 | VSS | power_in | Ground. |+| K8 | VSS | power_in | Ground. |+| K10 | VSS | power_in | Ground. |+| K12 | VSS | power_in | Ground. |+| K14 | VSS | power_in | Ground. |+| K16 | VSS | power_in | Ground. |+| L7 | VSS | power_in | Ground. |+| L9 | VSS | power_in | Ground. |+| L11 | VSS | power_in | Ground. |+| L13 | VSS | power_in | Ground. |+| L15 | VSS | power_in | Ground. |+| M1 | VSS | power_in | Ground. |+| M6 | VSS | power_in | Ground. |+| M8 | VSS | power_in | Ground. |+| M10 | VSS | power_in | Ground. |+| M12 | VSS | power_in | Ground. |+| M14 | VSS | power_in | Ground. |+| M16 | VSS | power_in | Ground. |+| M22 | VSS | power_in | Ground. |+| N7 | VSS | power_in | Ground. |+| N9 | VSS | power_in | Ground. |+| N11 | VSS | power_in | Ground. |+| N13 | VSS | power_in | Ground. |+| N15 | VSS | power_in | Ground. |+| N17 | VSS | power_in | Ground. |+| P6 | VSS | power_in | Ground. |+| P8 | VSS | power_in | Ground. |+| P10 | VSS | power_in | Ground. |+| P12 | VSS | power_in | Ground. |+| P14 | VSS | power_in | Ground. |+| P16 | VSS | power_in | Ground. |+| R5 | VSS | power_in | Ground. |+| R7 | VSS | power_in | Ground. |+| R9 | VSS | power_in | Ground. |+| R11 | VSS | power_in | Ground. |+| R13 | VSS | power_in | Ground. |+| R15 | VSS | power_in | Ground. |+| R17 | VSS | power_in | Ground. |+| T6 | VSS | power_in | Ground. |+| T8 | VSS | power_in | Ground. |+| T10 | VSS | power_in | Ground. |+| T12 | VSS | power_in | Ground. |+| T14 | VSS | power_in | Ground. |+| T16 | VSS | power_in | Ground. |+| T18 | VSS | power_in | Ground. |+| U5 | VSS | power_in | Ground. |+| U7 | VSS | power_in | Ground. |+| U9 | VSS | power_in | Ground. |+| U11 | VSS | power_in | Ground. |+| U13 | VSS | power_in | Ground. |+| U15 | VSS | power_in | Ground. |+| U17 | VSS | power_in | Ground. |+| V6 | VSS | power_in | Ground. |+| AB1 | VSS | power_in | Ground. |+| AB12 | VSS | power_in | Ground. |+| AB22 | VSS | power_in | Ground. |+| D8 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| D9 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| D10 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| E8 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| F8 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| F9 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| F10 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| J7 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| G6 | NC | unconnected | No connect; must be left unconnected for proper operation. |+| V15 | Reserved | passive | Reserved ball; must be pulled up via a 10 kΩ resistor for proper operation. |+| V16 | Reserved | passive | Reserved ball; must be pulled up via a 10 kΩ resistor for proper operation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | BGA-484 |+| Category | Embedded Processors & Controllers |+| Pins | 484 |++## CAD (KiCad official)++- Symbol: `AM3505AZER`+- Footprint: `Package_BGA:BGA-484_23.0x23.0mm_Layout22x22_P1.0mm`+- 3D model: BGA-484 (KiCad packages3D, STEP)+- 3D model files: `am3505azer-etched.step` / `am3505azer-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `am3505azer.step` / `am3505azer.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/am3517) (226 pp, sha256 `82e95be0c6355b7d`, retrieved 2026-10-12, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/am3505azer-datasheet.pdf)
am3505azer-hero.glbadded⋯ 1 unchanged line ⋯
am3505azer-hero.overlay.jsonadded+6376@@ -0,0 +1,6376 @@+{+ "spec": "adom-hero 1.4",+ "mpn": "AM3505AZER",+ "kind": "component + footprint reference art",+ "board_use": false,+ "plane_z_mm": -0.02,+ "units": "metre",+ "upAxis": "Z",+ "layers": {+ "pad_outlines": {+ "material": "Footprint pads - teal dashed outlines - 50 percent opacity",+ "rgba": [+ 0.0,+ 0.902,+ 0.863,+ 0.5+ ],+ "pads": 484,+ "span_mm": 21.5,+ "dash_mm": 0.45,+ "gap_mm": 0.27,+ "pad_stroke_mm": 0.09+ },+ "silkscreen": {+ "material": "Silkscreen reference lines - 30 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.3+ ],+ "footprint_items": 5,+ "pin1": {+ "source": "footprint silkscreen",+ "pad": "A1"+ }+ },+ "signal_names": {+ "material": "Signal names - 50 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.5+ ],+ "font": "DejaVu Sans Mono",+ "labels": 0,+ "sides": "top + mirrored underside (single-sided)",+ "omitted": "ball grid: labels omitted (they would sit under the body)",+ "fallback_to_pad_number": 0+ }+ },+ "align": {+ "ok": true,+ "centre_offset_mm": 0.004,+ "tolerance_mm": 1.72,+ "orientation_flipped": false,+ "contacts_bbox_mm": [+ -10.69,+ 10.697,+ -10.687,+ 10.687+ ],+ "pads_bbox_mm": [+ -10.75,+ 10.75,+ -10.75,+ 10.75+ ],+ "seating_z_mm": -0.015+ },+ "sources": {+ "glb": "am3505azer.glb",+ "glb_sha256": "428361b40c49293cf8e470bd95031a7e50aa8910851ce4881f24bea15c0e9c1d",+ "footprint": "am3505azer.kicad_mod",+ "footprint_sha256": "f53f744fa607cdc53882eda4219f873fad36d1eba952af0365e2a7dc45e380c9",+ "pins": "page.json component.pins",+ "pins_sha256": "ca9263962b4440c575ab6bb7fb9647da6b189c955dcd1ee0dff14dbbe6538d96"+ },+ "generator": "adom-wiki 1.7.69 (component_hero)",+ "labels": [],+ "pads": [+ {+ "number": "A1",+ "shape": "circle",+ "center_mm": [+ -10.5,+ -10.5+ ],+ "size_mm": [+ 0.5,+ 0.5+ ],+ "rot": 0.0+ },+ {+ "number": "A2",+ "shape": "circle",+ "center_mm": [+ -9.5,+ -10.5+ ],+ "size_mm": [+ 0.5,+ 0.5+ ],+ "rot": 0.0+ },+ {+ "number": "A3",+ "shape": "circle",+ "center_mm": [+ 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y="-251.46" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@79" x="17.78" y="-254" length="middle" direction="pwr" rot="R180"/>+ <pin name="mmc2_clk" x="17.78" y="-256.54" length="middle" direction="out" rot="R180"/>+ <pin name="mmc2_cmd" x="17.78" y="-259.08" length="middle" direction="io" rot="R180"/>+ <pin name="mmc2_dat7" x="17.78" y="-261.62" length="middle" direction="io" rot="R180"/>+ <pin name="mmc2_dat2" x="17.78" y="-264.16" length="middle" direction="io" rot="R180"/>+ <pin name="CAP_VDD_SRAM_MPU" x="17.78" y="-266.7" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@80" x="17.78" y="-269.24" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD_CORE@27" x="17.78" y="-271.78" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@81" x="17.78" y="-274.32" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD_CORE@28" x="17.78" y="-276.86" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@82" x="17.78" y="-279.4" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD_CORE@29" x="17.78" y="-281.94" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@83" x="17.78" y="-284.48" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD_CORE@30" x="17.78" y="-287.02" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@84" x="17.78" y="-289.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD_CORE@31" x="17.78" y="-292.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@85" x="17.78" y="-294.64" length="middle" direction="pwr" rot="R180"/>+ <pin name="sdrc_a2" x="17.78" y="-297.18" length="middle" direction="out" rot="R180"/>+ <pin name="sdrc_a1" x="17.78" y="-299.72" length="middle" direction="out" rot="R180"/>+ <pin name="sdrc_a0" x="17.78" y="-302.26" length="middle" direction="out" rot="R180"/>+ <pin name="ddr_padref" x="17.78" y="-304.8" length="middle" direction="pas" rot="R180"/>+ <pin name="VSS@86" x="17.78" y="-307.34" length="middle" direction="pwr" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="AM3505AZER" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="AM3505AZER" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="BGA-484_23.0x23.0mm_Layout22x22_P1.0mm">+ <connects>+ <connect gate="G$1" pin="VSS" pad="A1"/>+ <connect gate="G$1" pin="mcbsp4_dx" pad="A2"/>+ <connect gate="G$1" pin="mcbsp4_clkx" pad="A3"/>+ <connect gate="G$1" pin="mcbsp3_fsx" pad="A4"/>+ <connect gate="G$1" pin="uart2_cts" pad="A5"/>+ <connect gate="G$1" pin="usb0_dp" pad="A6"/>+ <connect gate="G$1" pin="usb0_drvvbus" pad="A7"/>+ <connect gate="G$1" pin="sys_32k" pad="A8"/>+ <connect gate="G$1" pin="sys_xtalout" pad="A9"/>+ <connect gate="G$1" pin="sys_xtalin" pad="A10"/>+ <connect gate="G$1" pin="VSS@2" pad="A11"/>+ <connect gate="G$1" pin="jtag_tms_tmsc" pad="A12"/>+ <connect gate="G$1" pin="dss_data20" pad="A13"/>+ <connect gate="G$1" pin="dss_data17" pad="A14"/>+ <connect gate="G$1" pin="dss_data16" pad="A15"/>+ <connect gate="G$1" pin="dss_data13" pad="A16"/>+ <connect gate="G$1" pin="dss_data4" pad="A17"/>+ <connect gate="G$1" pin="dss_data2" pad="A18"/>+ <connect gate="G$1" pin="dss_data1" pad="A19"/>+ <connect gate="G$1" pin="dss_data0" pad="A20"/>+ <connect gate="G$1" pin="VDDSHV" pad="A21"/>+ <connect gate="G$1" pin="VSS@3" pad="A22"/>+ <connect gate="G$1" pin="VDDSHV@2" pad="B1"/>+ <connect gate="G$1" pin="mcbsp4_fsx" pad="B2"/>+ <connect gate="G$1" pin="mcbsp4_dr" pad="B3"/>+ <connect gate="G$1" pin="mcbsp3_dr" pad="B4"/>+ <connect gate="G$1" pin="uart2_rts" pad="B5"/>+ <connect gate="G$1" pin="usb0_dm" pad="B6"/>+ <connect gate="G$1" pin="usb0_id" pad="B7"/>+ <connect gate="G$1" pin="sys_clkreq" pad="B8"/>+ <connect gate="G$1" pin="hdq_sio" pad="B9"/>+ <connect gate="G$1" pin="VSSOSC" pad="B10"/>+ <connect gate="G$1" pin="mcbsp1_clkr" pad="B11"/>+ <connect gate="G$1" pin="jtag_tdi" pad="B12"/>+ <connect gate="G$1" pin="dss_data21" pad="B13"/>+ <connect gate="G$1" pin="dss_data23" pad="B14"/>+ <connect gate="G$1" pin="dss_data15" pad="B15"/>+ <connect gate="G$1" pin="dss_data7" pad="B16"/>+ <connect gate="G$1" pin="dss_data8" pad="B17"/>+ <connect gate="G$1" pin="dss_data3" pad="B18"/>+ <connect gate="G$1" pin="dss_acbias" pad="B19"/>+ <connect gate="G$1" pin="dss_vsync" pad="B20"/>+ <connect gate="G$1" pin="dss_hsync" pad="B21"/>+ <connect gate="G$1" pin="dss_pclk" pad="B22"/>+ <connect gate="G$1" pin="sdrc_d6" pad="C1"/>+ <connect gate="G$1" pin="sdrc_d3" pad="C2"/>+ <connect gate="G$1" pin="sdrc_d2" pad="C3"/>+ <connect gate="G$1" pin="mcbsp3_dx" pad="C4"/>+ <connect gate="G$1" pin="mcbsp2_dr" pad="C5"/>+ <connect gate="G$1" pin="uart2_rx" pad="C6"/>+ <connect gate="G$1" pin="usb0_vbus" pad="C7"/>+ <connect gate="G$1" pin="mcbsp1_clkx" pad="C8"/>+ <connect gate="G$1" pin="mcbsp1_dr" pad="C9"/>+ <connect gate="G$1" pin="mcbsp1_dx" pad="C10"/>+ <connect gate="G$1" pin="mcbsp1_fsx" pad="C11"/>+ <connect gate="G$1" pin="jtag_rtck" pad="C12"/>+ <connect gate="G$1" pin="dss_data18" pad="C13"/>+ <connect gate="G$1" pin="dss_data22" pad="C14"/>+ <connect gate="G$1" pin="dss_data19" pad="C15"/>+ <connect gate="G$1" pin="dss_data10" pad="C16"/>+ <connect gate="G$1" pin="dss_data9" pad="C17"/>+ <connect gate="G$1" pin="dss_data5" pad="C18"/>+ <connect gate="G$1" pin="uart1_cts" pad="C19"/>+ <connect gate="G$1" pin="uart1_rx" pad="C20"/>+ <connect gate="G$1" pin="uart1_rts" pad="C21"/>+ <connect gate="G$1" pin="uart1_tx" pad="C22"/>+ <connect gate="G$1" pin="sdrc_d7" pad="D1"/>+ <connect gate="G$1" pin="sdrc_d5" pad="D2"/>+ <connect gate="G$1" pin="sdrc_d1" pad="D3"/>+ <connect gate="G$1" pin="mcbsp3_clkx" pad="D4"/>+ <connect gate="G$1" pin="mcbsp2_clkx" pad="D5"/>+ <connect gate="G$1" pin="uart2_tx" pad="D6"/>+ <connect gate="G$1" pin="VDDA1P8V_USBPHY" pad="D7"/>+ <connect gate="G$1" pin="NC" pad="D8"/>+ <connect gate="G$1" pin="NC@2" pad="D9"/>+ <connect gate="G$1" pin="NC@3" pad="D10"/>+ <connect gate="G$1" pin="mcbsp1_fsr" pad="D11"/>+ <connect gate="G$1" pin="jtag_tdo" pad="D12"/>+ <connect gate="G$1" pin="jtag_ntrst" pad="D13"/>+ <connect gate="G$1" pin="dss_data12" pad="D14"/>+ <connect gate="G$1" pin="dss_data14" pad="D15"/>+ <connect gate="G$1" pin="dss_data11" pad="D16"/>+ <connect gate="G$1" pin="dss_data6" pad="D17"/>+ <connect gate="G$1" pin="etk_d15" pad="D18"/>+ <connect gate="G$1" pin="etk_d14" pad="D19"/>+ <connect gate="G$1" pin="etk_d13" pad="D20"/>+ <connect gate="G$1" pin="etk_d9" pad="D21"/>+ <connect gate="G$1" pin="etk_d8" pad="D22"/>+ <connect gate="G$1" pin="sdrc_dqs0n" pad="E1"/>+ <connect gate="G$1" pin="sdrc_dqs0p" pad="E2"/>+ <connect gate="G$1" pin="sdrc_d0" pad="E3"/>+ <connect gate="G$1" pin="mcbsp2_dx" pad="E4"/>+ <connect gate="G$1" pin="mcbsp2_fsx" pad="E5"/>+ <connect gate="G$1" pin="VSS@4" pad="E6"/>+ <connect gate="G$1" pin="CAP_VDDA1_P2LDO_USBPHY" pad="E7"/>+ <connect gate="G$1" pin="NC@4" pad="E8"/>+ <connect gate="G$1" pin="sys_clkout1" pad="E9"/>+ <connect gate="G$1" pin="sys_clkout2" pad="E10"/>+ <connect gate="G$1" pin="mcbsp_clks" pad="E11"/>+ <connect gate="G$1" pin="jtag_emu1" pad="E12"/>+ <connect gate="G$1" pin="jtag_emu0" pad="E13"/>+ <connect gate="G$1" pin="jtag_tck" pad="E14"/>+ <connect gate="G$1" pin="VDDSHV@3" pad="E15"/>+ <connect gate="G$1" pin="VSS@5" pad="E16"/>+ <connect gate="G$1" pin="VDDSHV@4" pad="E17"/>+ <connect gate="G$1" pin="etk_d12" pad="E18"/>+ <connect gate="G$1" pin="etk_d4" pad="E19"/>+ <connect gate="G$1" pin="etk_d11" pad="E20"/>+ <connect gate="G$1" pin="etk_d7" pad="E21"/>+ <connect gate="G$1" pin="etk_d10" pad="E22"/>+ <connect gate="G$1" pin="sdrc_strben_dly0" pad="F1"/>+ <connect gate="G$1" pin="sdrc_strben0" pad="F2"/>+ <connect gate="G$1" pin="sdrc_d4" pad="F3"/>+ <connect gate="G$1" pin="sdrc_dm0" pad="F4"/>+ <connect gate="G$1" pin="VDDS" pad="F5"/>+ <connect gate="G$1" pin="VSS@6" pad="F6"/>+ <connect gate="G$1" pin="VDDA3P3V_USBPHY" pad="F7"/>+ <connect gate="G$1" pin="NC@5" pad="F8"/>+ <connect gate="G$1" pin="NC@6" pad="F9"/>+ <connect gate="G$1" pin="NC@7" pad="F10"/>+ <connect gate="G$1" pin="VDDS_DPLL_PER_CORE" pad="F11"/>+ <connect gate="G$1" pin="VDDSHV@5" pad="F12"/>+ <connect gate="G$1" pin="VSS@7" pad="F13"/>+ <connect gate="G$1" pin="VDDSHV@6" pad="F14"/>+ <connect gate="G$1" pin="VSS@8" pad="F15"/>+ <connect gate="G$1" pin="VDDS@2" pad="F16"/>+ <connect gate="G$1" pin="VSS@9" pad="F17"/>+ <connect gate="G$1" pin="VDDSHV@7" pad="F18"/>+ <connect gate="G$1" pin="etk_d6" pad="F19"/>+ <connect gate="G$1" pin="etk_d2" pad="F20"/>+ <connect gate="G$1" pin="etk_d5" pad="F21"/>+ <connect gate="G$1" pin="etk_d1" pad="F22"/>+ <connect gate="G$1" pin="sdrc_d13" pad="G1"/>+ <connect gate="G$1" pin="sdrc_d8" pad="G2"/>+ <connect gate="G$1" pin="sdrc_d9" pad="G3"/>+ <connect gate="G$1" pin="sdrc_d11" pad="G4"/>+ <connect gate="G$1" pin="VSS@10" pad="G5"/>+ <connect gate="G$1" pin="NC@8" pad="G6"/>+ <connect gate="G$1" pin="VSS@11" pad="G7"/>+ <connect gate="G$1" pin="VDDSHV@8" pad="G8"/>+ <connect gate="G$1" pin="VDDSOSC" pad="G9"/>+ <connect gate="G$1" pin="VDDSHV@9" pad="G10"/>+ <connect gate="G$1" pin="VSS@12" pad="G11"/>+ <connect gate="G$1" pin="VDDSHV@10" pad="G12"/>+ <connect gate="G$1" pin="VDDSHV@11" pad="G13"/>+ <connect gate="G$1" pin="VSS@13" pad="G14"/>+ <connect gate="G$1" pin="VDDS@3" pad="G15"/>+ <connect gate="G$1" pin="VSS@14" pad="G16"/>+ <connect gate="G$1" pin="VDDSHV@12" pad="G17"/>+ <connect gate="G$1" pin="VSS@15" pad="G18"/>+ <connect gate="G$1" pin="etk_d3" pad="G19"/>+ <connect gate="G$1" pin="etk_d0" pad="G20"/>+ <connect gate="G$1" pin="etk_ctl" pad="G21"/>+ <connect gate="G$1" pin="etk_clk" pad="G22"/>+ <connect gate="G$1" pin="sdrc_dqs1n" pad="H1"/>+ <connect gate="G$1" pin="sdrc_dqs1p" pad="H2"/>+ <connect gate="G$1" pin="sdrc_d10" pad="H3"/>+ <connect gate="G$1" pin="sdrc_d12" pad="H4"/>+ <connect gate="G$1" pin="VDDS@4" pad="H5"/>+ <connect gate="G$1" pin="VSS@16" pad="H6"/>+ <connect gate="G$1" pin="VSS@17" pad="H7"/>+ <connect gate="G$1" pin="VSS@18" pad="H8"/>+ <connect gate="G$1" pin="VSS@19" pad="H9"/>+ <connect gate="G$1" pin="VSS@20" pad="H10"/>+ <connect gate="G$1" pin="VSS@21" pad="H11"/>+ <connect gate="G$1" pin="VSS@22" pad="H12"/>+ <connect gate="G$1" pin="VSS@23" pad="H13"/>+ <connect gate="G$1" pin="VSS@24" pad="H14"/>+ <connect gate="G$1" pin="VSS@25" pad="H15"/>+ <connect gate="G$1" pin="VSS@26" pad="H16"/>+ <connect gate="G$1" pin="VSS@27" pad="H17"/>+ <connect gate="G$1" pin="VDDSHV@13" pad="H18"/>+ <connect gate="G$1" pin="mcspi2_cs1" pad="H19"/>+ <connect gate="G$1" pin="mcspi2_simo" pad="H20"/>+ <connect gate="G$1" pin="mcspi2_cs0" pad="H21"/>+ <connect gate="G$1" pin="mcspi2_somi" pad="H22"/>+ <connect gate="G$1" pin="sdrc_d15" pad="J1"/>+ <connect gate="G$1" pin="sdrc_dm1" pad="J2"/>+ <connect gate="G$1" pin="sdrc_d14" pad="J3"/>+ <connect gate="G$1" pin="sdrc_ncs0" pad="J4"/>+ <connect gate="G$1" pin="sdrc_ba2" pad="J5"/>+ <connect gate="G$1" pin="VDDS_SRAM_CORE_BG" pad="J6"/>+ <connect gate="G$1" pin="NC@9" pad="J7"/>+ <connect gate="G$1" pin="VDD_CORE" pad="J8"/>+ <connect gate="G$1" pin="VSS@28" pad="J9"/>+ <connect gate="G$1" pin="VDD_CORE@2" pad="J10"/>+ <connect gate="G$1" pin="VSS@29" pad="J11"/>+ <connect gate="G$1" pin="VDD_CORE@3" pad="J12"/>+ <connect gate="G$1" pin="VSS@30" pad="J13"/>+ <connect gate="G$1" pin="VDD_CORE@4" pad="J14"/>+ <connect gate="G$1" pin="VSS@31" pad="J15"/>+ <connect gate="G$1" pin="VDD_CORE@5" pad="J16"/>+ <connect gate="G$1" pin="VDDSHV@14" pad="J17"/>+ <connect gate="G$1" pin="mcspi1_somi" pad="J18"/>+ <connect gate="G$1" pin="mcspi1_cs2" pad="J19"/>+ <connect gate="G$1" pin="mcspi1_cs1" pad="J20"/>+ <connect gate="G$1" pin="mcspi1_cs3" pad="J21"/>+ <connect gate="G$1" pin="mcspi2_clk" pad="J22"/>+ <connect gate="G$1" pin="sdrc_nras" pad="K1"/>+ <connect gate="G$1" pin="sdrc_nwe" pad="K2"/>+ <connect gate="G$1" pin="sdrc_cke0" pad="K3"/>+ <connect gate="G$1" pin="sdrc_ncs1" pad="K4"/>+ <connect gate="G$1" pin="sdrc_ba1" pad="K5"/>+ <connect gate="G$1" pin="CAP_VDD_SRAM_CORE" pad="K6"/>+ <connect gate="G$1" pin="VDDS@5" pad="K7"/>+ <connect gate="G$1" pin="VSS@32" pad="K8"/>+ <connect gate="G$1" pin="VDD_CORE@6" pad="K9"/>+ <connect gate="G$1" pin="VSS@33" pad="K10"/>+ <connect gate="G$1" pin="VDD_CORE@7" pad="K11"/>+ <connect gate="G$1" pin="VSS@34" pad="K12"/>+ <connect gate="G$1" pin="VDD_CORE@8" pad="K13"/>+ <connect gate="G$1" pin="VSS@35" pad="K14"/>+ <connect gate="G$1" pin="VDD_CORE@9" pad="K15"/>+ <connect gate="G$1" pin="VSS@36" pad="K16"/>+ <connect gate="G$1" pin="VDDS_DPLL_MPU_USBHOST" pad="K17"/>+ <connect gate="G$1" pin="mcspi1_cs0" pad="K18"/>+ <connect gate="G$1" pin="mcspi1_simo" pad="K19"/>+ <connect gate="G$1" pin="mmc2_dat0" pad="K20"/>+ <connect gate="G$1" pin="mmc2_dat3" pad="K21"/>+ <connect gate="G$1" pin="mcspi1_clk" pad="K22"/>+ <connect gate="G$1" pin="sdrc_clk" pad="L1"/>+ <connect gate="G$1" pin="sdrc_nclk" pad="L2"/>+ <connect gate="G$1" pin="sdrc_ncas" pad="L3"/>+ <connect gate="G$1" pin="sdrc_ba0" pad="L4"/>+ <connect gate="G$1" pin="VREFSSTL" pad="L5"/>+ <connect gate="G$1" pin="VDDS@6" pad="L6"/>+ <connect gate="G$1" pin="VSS@37" pad="L7"/>+ <connect gate="G$1" pin="VDD_CORE@10" pad="L8"/>+ <connect gate="G$1" pin="VSS@38" pad="L9"/>+ <connect gate="G$1" pin="VDD_CORE@11" pad="L10"/>+ <connect gate="G$1" pin="VSS@39" pad="L11"/>+ <connect gate="G$1" pin="VDD_CORE@12" pad="L12"/>+ <connect gate="G$1" pin="VSS@40" pad="L13"/>+ <connect gate="G$1" pin="VDD_CORE@13" pad="L14"/>+ <connect gate="G$1" pin="VSS@41" pad="L15"/>+ <connect gate="G$1" pin="VDDS@7" pad="L16"/>+ <connect gate="G$1" pin="VDDS_SRAM_MPU" pad="L17"/>+ <connect gate="G$1" pin="mmc2_dat4" pad="L18"/>+ <connect gate="G$1" pin="mmc2_dat1" pad="L19"/>+ <connect gate="G$1" pin="mmc2_dat5" pad="L20"/>+ <connect gate="G$1" pin="mmc2_dat6" pad="L21"/>+ <connect gate="G$1" pin="VDDSHV@15" pad="L22"/>+ <connect gate="G$1" pin="VSS@42" pad="AB22"/>+ <connect gate="G$1" pin="ccdc_pclk" pad="AB21"/>+ <connect gate="G$1" pin="sys_boot1" pad="AB20"/>+ <connect gate="G$1" pin="sys_boot0" pad="AB19"/>+ <connect gate="G$1" pin="sys_nirq" pad="AB18"/>+ <connect gate="G$1" pin="i2c1_sda" pad="AB17"/>+ <connect gate="G$1" pin="hecc1_rxd" pad="AB16"/>+ <connect gate="G$1" pin="hecc1_txd" pad="AB15"/>+ <connect gate="G$1" pin="gpmc_noe" pad="AB14"/>+ <connect gate="G$1" pin="gpmc_clk" pad="AB13"/>+ <connect gate="G$1" pin="VSS@43" pad="AB12"/>+ <connect gate="G$1" pin="VDDSHV@16" pad="AB11"/>+ <connect gate="G$1" pin="gpmc_d10" pad="AB10"/>+ <connect gate="G$1" pin="gpmc_d9" pad="AB9"/>+ <connect gate="G$1" pin="gpmc_d6" pad="AB8"/>+ <connect gate="G$1" pin="gpmc_a9" pad="AB7"/>+ <connect gate="G$1" pin="gpmc_a6" pad="AB6"/>+ <connect gate="G$1" pin="gpmc_a5" pad="AB5"/>+ <connect gate="G$1" pin="gpmc_a3" pad="AB4"/>+ <connect gate="G$1" pin="sdrc_dm3" pad="AB3"/>+ <connect gate="G$1" pin="sdrc_d31" pad="AB2"/>+ <connect gate="G$1" pin="VSS@44" pad="AB1"/>+ <connect gate="G$1" pin="VDDSHV@17" pad="AA22"/>+ <connect gate="G$1" pin="ccdc_field" pad="AA21"/>+ <connect gate="G$1" pin="sys_boot7" pad="AA20"/>+ <connect gate="G$1" pin="sys_boot3" pad="AA19"/>+ <connect gate="G$1" pin="sys_nrespwron" pad="AA18"/>+ <connect gate="G$1" pin="i2c1_scl" pad="AA17"/>+ <connect gate="G$1" pin="gpmc_wait1" pad="AA16"/>+ <connect gate="G$1" pin="gpmc_nwe" pad="AA15"/>+ <connect gate="G$1" pin="gpmc_nadv_ale" pad="AA14"/>+ <connect gate="G$1" pin="uart3_rx_irrx" pad="AA13"/>+ <connect gate="G$1" pin="gpmc_ncs6" pad="AA12"/>+ <connect gate="G$1" pin="gpmc_ncs4" pad="AA11"/>+ <connect gate="G$1" pin="gpmc_d12" pad="AA10"/>+ <connect gate="G$1" pin="gpmc_d3" pad="AA9"/>+ <connect gate="G$1" pin="gpmc_d5" pad="AA8"/>+ <connect gate="G$1" pin="gpmc_d0" pad="AA7"/>+ <connect gate="G$1" pin="gpmc_a7" pad="AA6"/>+ <connect gate="G$1" pin="gpmc_a4" pad="AA5"/>+ <connect gate="G$1" pin="sdrc_d30" pad="AA4"/>+ <connect gate="G$1" pin="sdrc_d29" pad="AA3"/>+ <connect gate="G$1" pin="sdrc_d28" pad="AA2"/>+ <connect gate="G$1" pin="VDDS@8" pad="AA1"/>+ <connect gate="G$1" pin="ccdc_vd" pad="Y22"/>+ <connect gate="G$1" pin="ccdc_hd" pad="Y21"/>+ <connect gate="G$1" pin="sys_boot8" pad="Y20"/>+ <connect gate="G$1" pin="sys_boot5" pad="Y19"/>+ <connect gate="G$1" pin="sys_nreswarm" pad="Y18"/>+ <connect gate="G$1" pin="i2c2_scl" pad="Y17"/>+ <connect gate="G$1" pin="i2c2_sda" pad="Y16"/>+ <connect gate="G$1" pin="gpmc_nbe1" pad="Y15"/>+ <connect gate="G$1" pin="gpmc_wait2" pad="Y14"/>+ <connect gate="G$1" pin="uart3_tx_irtx" pad="Y13"/>+ <connect gate="G$1" pin="gpmc_ncs2" pad="Y12"/>+ <connect gate="G$1" pin="gpmc_ncs1" pad="Y11"/>+ <connect gate="G$1" pin="gpmc_ncs0" pad="Y10"/>+ <connect gate="G$1" pin="gpmc_d13" pad="Y9"/>+ <connect gate="G$1" pin="gpmc_d4" pad="Y8"/>+ <connect gate="G$1" pin="gpmc_d1" pad="Y7"/>+ <connect gate="G$1" pin="gpmc_a10" pad="Y6"/>+ <connect gate="G$1" pin="gpmc_a2" pad="Y5"/>+ <connect gate="G$1" pin="sdrc_d27" pad="Y4"/>+ <connect gate="G$1" pin="sdrc_d26" pad="Y3"/>+ <connect gate="G$1" pin="sdrc_dqs3n" pad="Y2"/>+ <connect gate="G$1" pin="sdrc_dqs3p" pad="Y1"/>+ <connect gate="G$1" pin="ccdc_data0" pad="W22"/>+ <connect gate="G$1" pin="ccdc_wen" pad="W21"/>+ <connect gate="G$1" pin="ccdc_data1" pad="W20"/>+ <connect gate="G$1" pin="sys_boot6" pad="W19"/>+ <connect gate="G$1" pin="sys_boot2" pad="W18"/>+ <connect gate="G$1" pin="i2c3_sda" pad="W17"/>+ <connect gate="G$1" pin="i2c3_scl" pad="W16"/>+ <connect gate="G$1" pin="uart3_cts_rctx" pad="W15"/>+ <connect gate="G$1" pin="gpmc_nwp" pad="W14"/>+ <connect gate="G$1" pin="uart3_rts_sd" pad="W13"/>+ <connect gate="G$1" pin="gpmc_ncs5" pad="W12"/>+ <connect gate="G$1" pin="gpmc_nbe0_cle" pad="W11"/>+ <connect gate="G$1" pin="gpmc_d8" pad="W10"/>+ <connect gate="G$1" pin="gpmc_d11" pad="W9"/>+ <connect gate="G$1" pin="gpmc_d7" pad="W8"/>+ <connect gate="G$1" pin="gpmc_d2" pad="W7"/>+ <connect gate="G$1" pin="gpmc_a8" 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gate="G$1" pin="VSS@75" pad="N13"/>+ <connect gate="G$1" pin="VDD_CORE@24" pad="N12"/>+ <connect gate="G$1" pin="VSS@76" pad="N11"/>+ <connect gate="G$1" pin="VDD_CORE@25" pad="N10"/>+ <connect gate="G$1" pin="VSS@77" pad="N9"/>+ <connect gate="G$1" pin="VDD_CORE@26" pad="N8"/>+ <connect gate="G$1" pin="VSS@78" pad="N7"/>+ <connect gate="G$1" pin="VDDS@15" pad="N6"/>+ <connect gate="G$1" pin="VDDS@16" pad="N5"/>+ <connect gate="G$1" pin="sdrc_a5" pad="N4"/>+ <connect gate="G$1" pin="sdrc_a3" pad="N3"/>+ <connect gate="G$1" pin="sdrc_a4" pad="N2"/>+ <connect gate="G$1" pin="VDDS@17" pad="N1"/>+ <connect gate="G$1" pin="VSS@79" pad="M22"/>+ <connect gate="G$1" pin="mmc2_clk" pad="M21"/>+ <connect gate="G$1" pin="mmc2_cmd" pad="M20"/>+ <connect gate="G$1" pin="mmc2_dat7" pad="M19"/>+ <connect gate="G$1" pin="mmc2_dat2" pad="M18"/>+ <connect gate="G$1" pin="CAP_VDD_SRAM_MPU" pad="M17"/>+ <connect gate="G$1" pin="VSS@80" pad="M16"/>+ <connect gate="G$1" pin="VDD_CORE@27" pad="M15"/>+ <connect gate="G$1" pin="VSS@81" pad="M14"/>+ <connect gate="G$1" pin="VDD_CORE@28" pad="M13"/>+ <connect gate="G$1" pin="VSS@82" pad="M12"/>+ <connect gate="G$1" pin="VDD_CORE@29" pad="M11"/>+ <connect gate="G$1" pin="VSS@83" pad="M10"/>+ <connect gate="G$1" pin="VDD_CORE@30" pad="M9"/>+ <connect gate="G$1" pin="VSS@84" pad="M8"/>+ <connect gate="G$1" pin="VDD_CORE@31" pad="M7"/>+ <connect gate="G$1" pin="VSS@85" pad="M6"/>+ <connect gate="G$1" pin="sdrc_a2" pad="M5"/>+ <connect gate="G$1" pin="sdrc_a1" pad="M4"/>+ <connect gate="G$1" pin="sdrc_a0" pad="M3"/>+ <connect gate="G$1" pin="ddr_padref" pad="M2"/>+ <connect gate="G$1" pin="VSS@86" pad="M1"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
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Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of BGA-484_23.0x23.0mm_Layout22x22_P1.0mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'BGA-484_23.0x23.0mm_Layout22x22_P1.0mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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_ITEM('color',(#10815),#8773);+#11646=STYLED_ITEM('color',(#10815),#8786);+#11647=STYLED_ITEM('color',(#10815),#8799);+#11648=STYLED_ITEM('color',(#10815),#8812);+#11649=STYLED_ITEM('color',(#10815),#8825);+#11650=STYLED_ITEM('color',(#10815),#8838);+#11651=STYLED_ITEM('color',(#10815),#8851);+#11652=STYLED_ITEM('color',(#10815),#8864);+#11653=STYLED_ITEM('color',(#10815),#8877);+#11654=STYLED_ITEM('color',(#10815),#8890);+#11655=STYLED_ITEM('color',(#10815),#8903);+#11656=STYLED_ITEM('color',(#10815),#8916);+#11657=STYLED_ITEM('color',(#10815),#8929);+#11658=STYLED_ITEM('color',(#10815),#8942);+#11659=STYLED_ITEM('color',(#10815),#8955);+#11660=STYLED_ITEM('color',(#10815),#8968);+#11661=STYLED_ITEM('color',(#10815),#8981);+#11662=STYLED_ITEM('color',(#10815),#8994);+#11663=STYLED_ITEM('color',(#10815),#9007);+#11664=STYLED_ITEM('color',(#10815),#9020);+#11665=STYLED_ITEM('color',(#10815),#9033);+#11666=STYLED_ITEM('color',(#10815),#9046);+#11667=STYLED_ITEM('color',(#10815),#9059);+#11668=STYLED_ITEM('color',(#10815),#9072);+#11669=STYLED_ITEM('color',(#10815),#9085);+#11670=STYLED_ITEM('color',(#10815),#9098);+#11671=STYLED_ITEM('color',(#10815),#9111);+#11672=STYLED_ITEM('color',(#10815),#9124);+#11673=STYLED_ITEM('color',(#10815),#9137);+#11674=STYLED_ITEM('color',(#10815),#9150);+#11675=STYLED_ITEM('color',(#10815),#9163);+#11676=STYLED_ITEM('color',(#10815),#9176);+#11677=STYLED_ITEM('color',(#10815),#9189);+#11678=STYLED_ITEM('color',(#10815),#9202);+#11679=STYLED_ITEM('color',(#10815),#9215);+#11680=STYLED_ITEM('color',(#10815),#9228);+#11681=STYLED_ITEM('color',(#10815),#9241);+#11682=STYLED_ITEM('color',(#10815),#9254);+#11683=STYLED_ITEM('color',(#10815),#9267);+#11684=STYLED_ITEM('color',(#10815),#9280);+#11685=STYLED_ITEM('color',(#10815),#9293);+#11686=STYLED_ITEM('color',(#10815),#9306);+#11687=STYLED_ITEM('color',(#10815),#9319);+#11688=STYLED_ITEM('color',(#10815),#9332);+#11689=STYLED_ITEM('color',(#10815),#9345);+#11690=STYLED_ITEM('color',(#10815),#9358);+#11691=STYLED_ITEM('color',(#10815),#9371);+#11692=STYLED_ITEM('color',(#10815),#9384);+#11693=STYLED_ITEM('color',(#10815),#9397);+#11694=STYLED_ITEM('color',(#10815),#9410);+#11695=STYLED_ITEM('color',(#10815),#9423);+#11696=STYLED_ITEM('color',(#10815),#9436);+#11697=STYLED_ITEM('color',(#10815),#9449);+#11698=STYLED_ITEM('color',(#10815),#9462);+#11699=STYLED_ITEM('color',(#10815),#9475);+#11700=STYLED_ITEM('color',(#10815),#9488);+#11701=STYLED_ITEM('color',(#10815),#9501);+#11702=STYLED_ITEM('color',(#10815),#9514);+#11703=STYLED_ITEM('color',(#10815),#9527);+#11704=STYLED_ITEM('color',(#10815),#9540);+#11705=STYLED_ITEM('color',(#10815),#9553);+#11706=STYLED_ITEM('color',(#10815),#9566);+#11707=STYLED_ITEM('color',(#10815),#9579);+#11708=STYLED_ITEM('color',(#10815),#9592);+#11709=STYLED_ITEM('color',(#10815),#9605);+#11710=STYLED_ITEM('color',(#10815),#9618);+#11711=STYLED_ITEM('color',(#10815),#9631);+#11712=STYLED_ITEM('color',(#10815),#9644);+#11713=STYLED_ITEM('color',(#10815),#9657);+#11714=STYLED_ITEM('color',(#10815),#9670);+#11715=STYLED_ITEM('color',(#10815),#9683);+#11716=STYLED_ITEM('color',(#10815),#9696);+#11717=STYLED_ITEM('color',(#10815),#9709);+#11718=STYLED_ITEM('color',(#10815),#9722);+#11719=STYLED_ITEM('color',(#10815),#9735);+#11720=STYLED_ITEM('color',(#10815),#9748);+#11721=STYLED_ITEM('color',(#10815),#9761);+#11722=STYLED_ITEM('color',(#10815),#9774);+#11723=STYLED_ITEM('color',(#10815),#9787);+#11724=STYLED_ITEM('color',(#10815),#9800);+#11725=STYLED_ITEM('color',(#10815),#9813);+#11726=STYLED_ITEM('color',(#10815),#9826);+#11727=STYLED_ITEM('color',(#10815),#9839);+#11728=STYLED_ITEM('color',(#10815),#9852);+#11729=STYLED_ITEM('color',(#10815),#9865);+#11730=STYLED_ITEM('color',(#10815),#9878);+#11731=STYLED_ITEM('color',(#10815),#9891);+#11732=STYLED_ITEM('color',(#10815),#9904);+#11733=STYLED_ITEM('color',(#10815),#9917);+#11734=STYLED_ITEM('color',(#10815),#9930);+#11735=STYLED_ITEM('color',(#10815),#9943);+#11736=STYLED_ITEM('color',(#10815),#9956);+#11737=STYLED_ITEM('color',(#10815),#9969);+#11738=STYLED_ITEM('color',(#10815),#9982);+#11739=STYLED_ITEM('color',(#10815),#9995);+#11740=STYLED_ITEM('color',(#10815),#10008);+#11741=STYLED_ITEM('color',(#10815),#10021);+#11742=STYLED_ITEM('color',(#10815),#10034);+#11743=STYLED_ITEM('color',(#10815),#10047);+#11744=STYLED_ITEM('color',(#10815),#10060);+#11745=STYLED_ITEM('color',(#10815),#10073);+#11746=STYLED_ITEM('color',(#10815),#10086);+#11747=STYLED_ITEM('color',(#10815),#10099);+#11748=STYLED_ITEM('color',(#10815),#10112);+#11749=STYLED_ITEM('color',(#10815),#10125);+#11750=STYLED_ITEM('color',(#10815),#10138);+#11751=STYLED_ITEM('color',(#10815),#10151);+#11752=STYLED_ITEM('color',(#10815),#10164);+#11753=STYLED_ITEM('color',(#10815),#10177);+#11754=STYLED_ITEM('color',(#10815),#10190);+#11755=STYLED_ITEM('color',(#10815),#10203);+#11756=STYLED_ITEM('color',(#10815),#10216);+#11757=STYLED_ITEM('color',(#10815),#10229);+#11758=STYLED_ITEM('color',(#10815),#10242);+#11759=STYLED_ITEM('color',(#10815),#10255);+#11760=STYLED_ITEM('color',(#10815),#10268);+#11761=STYLED_ITEM('color',(#10815),#10281);+#11762=STYLED_ITEM('color',(#10815),#10294);+#11763=STYLED_ITEM('color',(#10815),#10307);+#11764=STYLED_ITEM('color',(#10815),#10320);+#11765=STYLED_ITEM('color',(#10815),#10333);+#11766=STYLED_ITEM('color',(#10815),#10346);+#11767=STYLED_ITEM('color',(#10815),#10359);+#11768=STYLED_ITEM('color',(#10815),#10372);+#11769=STYLED_ITEM('color',(#10815),#10385);+#11770=STYLED_ITEM('color',(#10815),#10398);+#11771=STYLED_ITEM('color',(#10815),#10411);+#11772=STYLED_ITEM('color',(#10815),#10424);+#11773=STYLED_ITEM('color',(#10815),#10437);+#11774=STYLED_ITEM('color',(#10815),#10450);+#11775=STYLED_ITEM('color',(#10815),#10463);+#11776=STYLED_ITEM('color',(#10815),#10476);+#11777=STYLED_ITEM('color',(#10815),#10489);+#11778=STYLED_ITEM('color',(#10815),#10502);+#11779=STYLED_ITEM('color',(#10815),#10515);+#11780=STYLED_ITEM('color',(#10815),#10528);+#11781=STYLED_ITEM('color',(#10815),#10541);+#11782=STYLED_ITEM('color',(#10815),#10554);+#11783=STYLED_ITEM('color',(#10815),#10567);+#11784=STYLED_ITEM('color',(#10815),#10580);+#11785=STYLED_ITEM('color',(#10815),#10593);+#11786=STYLED_ITEM('color',(#10815),#10606);+#11787=STYLED_ITEM('color',(#10815),#10619);+#11788=STYLED_ITEM('color',(#10815),#10632);+#11789=STYLED_ITEM('color',(#10815),#10645);+#11790=STYLED_ITEM('color',(#10815),#10658);+#11791=STYLED_ITEM('color',(#10815),#10671);+#11792=STYLED_ITEM('color',(#10815),#10684);+#11793=STYLED_ITEM('color',(#10815),#10697);+#11794=STYLED_ITEM('color',(#10815),#10710);+#11795=STYLED_ITEM('color',(#10815),#10723);+#11796=STYLED_ITEM('color',(#10815),#10736);+#11797=STYLED_ITEM('color',(#10815),#10749);+#11798=STYLED_ITEM('color',(#10815),#10762);+#11799=STYLED_ITEM('color',(#10815),#10775);+#11800=STYLED_ITEM('color',(#11308),#10788);+ENDSEC;+END-ISO-10303-21;
docs/am3505azer-datasheet.pdfadded⋯ 1 unchanged line ⋯
docs/hero.pngadded⋯ 1 unchanged line ⋯
package.jsonadded+2474@@ -0,0 +1,3050 @@+{+ "slug": "am3505azer",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), BGA-484. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "am3505azer",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "am3505azer.kicad_sym",+ "am3505azer.kicad_mod",+ "am3505azer.glb",+ "am3505azer.step",+ "am3505azer.lbr",+ "docs/hero.png",+ "docs/am3505azer-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "am3505azer-hero.glb",+ "am3505azer-hero.overlay.json"+ ],+ "component": {+ "mpn": "AM3505AZER",+ "manufacturer": "Texas Instruments",+ "package": "BGA-484",+ "pin_count": 484,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/am3517",+ "parts": {+ "symbol": "am3505azer.kicad_sym",+ "footprint": "am3505azer.kicad_mod",+ "model_3d": "am3505azer-hero.glb",+ "model_3d_plain": "am3505azer.glb",+ "model_3d_step": "am3505azer-etched.step",+ "model_3d_step_plain": "am3505azer.step",+ "lbr": "am3505azer.lbr"+ },+ "distributor_links": {+ "lcsc": "C1555428",+ "digikey": "296-39681-ND",+ "mouser": "595-AM3505AZER"+ },+ "distributor_check": {+ "checked_at": "2026-10-12T02:28:30Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-39681-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-AM3505AZER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "E3",+ "name": "sdrc_d0",+ "type": "bidirectional",+ "description": "SDRC data bit 0 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "D3",+ "name": "sdrc_d1",+ "type": "bidirectional",+ "description": "SDRC data bit 1 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "C3",+ "name": "sdrc_d2",+ "type": "bidirectional",+ "description": "SDRC data bit 2 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "C2",+ "name": "sdrc_d3",+ "type": "bidirectional",+ "description": "SDRC data bit 3 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "F3",+ "name": "sdrc_d4",+ "type": "bidirectional",+ "description": "SDRC data bit 4 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "D2",+ "name": "sdrc_d5",+ "type": "bidirectional",+ "description": "SDRC data bit 5 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "C1",+ "name": "sdrc_d6",+ "type": "bidirectional",+ "description": "SDRC data bit 6 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "D1",+ "name": "sdrc_d7",+ "type": "bidirectional",+ "description": "SDRC data bit 7 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "G2",+ "name": "sdrc_d8",+ "type": "bidirectional",+ "description": "SDRC data bit 8 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "G3",+ "name": "sdrc_d9",+ "type": "bidirectional",+ "description": "SDRC data bit 9 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "H3",+ "name": "sdrc_d10",+ "type": "bidirectional",+ "description": "SDRC data bit 10 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "G4",+ "name": "sdrc_d11",+ "type": "bidirectional",+ "description": "SDRC data bit 11 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "H4",+ "name": "sdrc_d12",+ "type": "bidirectional",+ "description": "SDRC data bit 12 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "G1",+ "name": "sdrc_d13",+ "type": "bidirectional",+ "description": "SDRC data bit 13 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "J3",+ "name": "sdrc_d14",+ "type": "bidirectional",+ "description": "SDRC data bit 14 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "J1",+ "name": "sdrc_d15",+ "type": "bidirectional",+ "description": "SDRC data bit 15 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "T3",+ "name": "sdrc_d16",+ "type": "bidirectional",+ "description": "SDRC data bit 16 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "U3",+ "name": "sdrc_d17",+ "type": "bidirectional",+ "description": "SDRC data bit 17 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "U4",+ "name": "sdrc_d18",+ "type": "bidirectional",+ "description": "SDRC data bit 18 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "V4",+ "name": "sdrc_d19",+ "type": "bidirectional",+ "description": "SDRC data bit 19 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "V1",+ "name": "sdrc_d20",+ "type": "bidirectional",+ "description": "SDRC data bit 20 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "V2",+ "name": "sdrc_d21",+ "type": "bidirectional",+ "description": "SDRC data bit 21 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "V5",+ "name": "sdrc_d22",+ "type": "bidirectional",+ "description": "SDRC data bit 22 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "V3",+ "name": "sdrc_d23",+ "type": "bidirectional",+ "description": "SDRC data bit 23 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "W3",+ "name": "sdrc_d24",+ "type": "bidirectional",+ "description": "SDRC data bit 24 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "W4",+ "name": "sdrc_d25",+ "type": "bidirectional",+ "description": "SDRC data bit 25 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "Y3",+ "name": "sdrc_d26",+ "type": "bidirectional",+ "description": "SDRC data bit 26 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "Y4",+ "name": "sdrc_d27",+ "type": "bidirectional",+ "description": "SDRC data bit 27 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "AA2",+ "name": "sdrc_d28",+ "type": "bidirectional",+ "description": "SDRC data bit 28 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "AA3",+ "name": "sdrc_d29",+ "type": "bidirectional",+ "description": "SDRC data bit 29 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "AA4",+ "name": "sdrc_d30",+ "type": "bidirectional",+ "description": "SDRC data bit 30 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "AB2",+ "name": "sdrc_d31",+ "type": "bidirectional",+ "description": "SDRC data bit 31 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD."+ },+ {+ "number": "L4",+ "name": "sdrc_ba0",+ "type": "output",+ "description": "SDRC bank address bit 0 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "K5",+ "name": "sdrc_ba1",+ "type": "output",+ "description": "SDRC bank address bit 1 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "J5",+ "name": "sdrc_ba2",+ "type": "output",+ "description": "SDRC bank address bit 2 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "M3",+ "name": "sdrc_a0",+ "type": "output",+ "description": "SDRC address bit 0 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "M4",+ "name": "sdrc_a1",+ "type": "output",+ "description": "SDRC address bit 1 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "M5",+ "name": "sdrc_a2",+ "type": "output",+ "description": "SDRC address bit 2 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "N3",+ "name": "sdrc_a3",+ "type": "output",+ "description": "SDRC address bit 3 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "N2",+ "name": "sdrc_a4",+ "type": "output",+ "description": "SDRC address bit 4 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "N4",+ "name": "sdrc_a5",+ "type": "output",+ "description": "SDRC address bit 5 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "P3",+ "name": "sdrc_a6",+ "type": "output",+ "description": "SDRC address bit 6 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "P2",+ "name": "sdrc_a7",+ "type": "output",+ "description": "SDRC address bit 7 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "P1",+ "name": "sdrc_a8",+ "type": "output",+ "description": "SDRC address bit 8 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "P4",+ "name": "sdrc_a9",+ "type": "output",+ "description": "SDRC address bit 9 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "R1",+ "name": "sdrc_a10",+ "type": "output",+ "description": "SDRC address bit 10 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "R2",+ "name": "sdrc_a11",+ "type": "output",+ "description": "SDRC address bit 11 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "R3",+ "name": "sdrc_a12",+ "type": "output",+ "description": "SDRC address bit 12 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "R4",+ "name": "sdrc_a13",+ "type": "output",+ "description": "SDRC address bit 13 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "T2",+ "name": "sdrc_a14",+ "type": "output",+ "description": "SDRC address bit 14 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "J4",+ "name": "sdrc_ncs0",+ "type": "output",+ "description": "SDRC chip select 0 (active low) output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "K4",+ "name": "sdrc_ncs1",+ "type": "output",+ "description": "SDRC chip select 1 (active low) output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "L1",+ "name": "sdrc_clk",+ "type": "output",+ "description": "SDRC differential clock output (true) on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "L2",+ "name": "sdrc_nclk",+ "type": "output",+ "description": "SDRC differential clock output (complement) on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "K3",+ "name": "sdrc_cke0",+ "type": "output",+ "description": "SDRC clock enable 0 on VDDS (1.8 V), 8 pF load, reset state 0 with pulldown; mode 7 provides sdrc_cke0_safe."+ },+ {+ "number": "K1",+ "name": "sdrc_nras",+ "type": "output",+ "description": "SDRC row address strobe output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "L3",+ "name": "sdrc_ncas",+ "type": "output",+ "description": "SDRC column address strobe output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "K2",+ "name": "sdrc_nwe",+ "type": "output",+ "description": "SDRC write enable output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "F4",+ "name": "sdrc_dm0",+ "type": "output",+ "description": "SDRC data mask 0 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "J2",+ "name": "sdrc_dm1",+ "type": "output",+ "description": "SDRC data mask 1 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "T4",+ "name": "sdrc_dm2",+ "type": "output",+ "description": "SDRC data mask 2 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "AB3",+ "name": "sdrc_dm3",+ "type": "output",+ "description": "SDRC data mask 3 output on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "E2",+ "name": "sdrc_dqs0p",+ "type": "bidirectional",+ "description": "SDRC data strobe 0 true on VDDS (1.8 V), reset state Z, hysteresis enabled."+ },+ {+ "number": "H2",+ "name": "sdrc_dqs1p",+ "type": "bidirectional",+ "description": "SDRC data strobe 1 true on VDDS (1.8 V), reset state Z, hysteresis enabled."+ },+ {+ "number": "U1",+ "name": "sdrc_dqs2p",+ "type": "bidirectional",+ "description": "SDRC data strobe 2 true on VDDS (1.8 V), reset state Z, hysteresis enabled."+ },+ {+ "number": "Y1",+ "name": "sdrc_dqs3p",+ "type": "bidirectional",+ "description": "SDRC data strobe 3 true on VDDS (1.8 V), reset state Z, hysteresis enabled."+ },+ {+ "number": "E1",+ "name": "sdrc_dqs0n",+ "type": "bidirectional",+ "description": "SDRC data strobe 0 complement on VDDS (1.8 V), reset state Z."+ },+ {+ "number": "H1",+ "name": "sdrc_dqs1n",+ "type": "bidirectional",+ "description": "SDRC data strobe 1 complement on VDDS (1.8 V), reset state Z."+ },+ {+ "number": "U2",+ "name": "sdrc_dqs2n",+ "type": "bidirectional",+ "description": "SDRC data strobe 2 complement on VDDS (1.8 V), reset state Z."+ },+ {+ "number": "Y2",+ "name": "sdrc_dqs3n",+ "type": "bidirectional",+ "description": "SDRC data strobe 3 complement on VDDS (1.8 V), reset state Z."+ },+ {+ "number": "T1",+ "name": "sdrc_odt",+ "type": "output",+ "description": "SDRC on-die termination control on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "F2",+ "name": "sdrc_strben0",+ "type": "output",+ "description": "SDRC read strobe enable 0 on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "F1",+ "name": "sdrc_strben_dly0",+ "type": "output",+ "description": "SDRC read strobe enable delayed 0 on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "W1",+ "name": "sdrc_strben1",+ "type": "output",+ "description": "SDRC read strobe enable 1 on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "W2",+ "name": "sdrc_strben_dly1",+ "type": "output",+ "description": "SDRC read strobe enable delayed 1 on VDDS (1.8 V), 8 pF load, reset state Z."+ },+ {+ "number": "W5",+ "name": "gpmc_a1",+ "type": "output",+ "description": "GPMC address bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "Y5",+ "name": "gpmc_a2",+ "type": "output",+ "description": "GPMC address bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "AB4",+ "name": "gpmc_a3",+ "type": "output",+ "description": "GPMC address bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "AA5",+ "name": "gpmc_a4",+ "type": "output",+ "description": "GPMC address bit 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "AB5",+ "name": "gpmc_a5",+ "type": "output",+ "description": "GPMC address bit 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "AB6",+ "name": "gpmc_a6",+ "type": "output",+ "description": "GPMC address bit 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "AA6",+ "name": "gpmc_a7",+ "type": "output",+ "description": "GPMC address bit 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "W6",+ "name": "gpmc_a8",+ "type": "output",+ "description": "GPMC address bit 8 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "AB7",+ "name": "gpmc_a9",+ "type": "output",+ "description": "GPMC address bit 9 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq2 in mode 1."+ },+ {+ "number": "Y6",+ "name": "gpmc_a10",+ "type": "output",+ "description": "GPMC address bit 10 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq3 in mode 1."+ },+ {+ "number": "AA7",+ "name": "gpmc_d0",+ "type": "bidirectional",+ "description": "GPMC data bit 0 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, internal PU/PD."+ },+ {+ "number": "Y7",+ "name": "gpmc_d1",+ "type": "bidirectional",+ "description": "GPMC data bit 1 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "W7",+ "name": "gpmc_d2",+ "type": "bidirectional",+ "description": "GPMC data bit 2 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "AA9",+ "name": "gpmc_d3",+ "type": "bidirectional",+ "description": "GPMC data bit 3 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "Y8",+ "name": "gpmc_d4",+ "type": "bidirectional",+ "description": "GPMC data bit 4 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "AA8",+ "name": "gpmc_d5",+ "type": "bidirectional",+ "description": "GPMC data bit 5 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "AB8",+ "name": "gpmc_d6",+ "type": "bidirectional",+ "description": "GPMC data bit 6 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "W8",+ "name": "gpmc_d7",+ "type": "bidirectional",+ "description": "GPMC data bit 7 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "W10",+ "name": "gpmc_d8",+ "type": "bidirectional",+ "description": "GPMC data bit 8 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_44 in mode 4."+ },+ {+ "number": "AB9",+ "name": "gpmc_d9",+ "type": "bidirectional",+ "description": "GPMC data bit 9 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_45 in mode 4."+ },+ {+ "number": "AB10",+ "name": "gpmc_d10",+ "type": "bidirectional",+ "description": "GPMC data bit 10 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_46 in mode 4."+ },+ {+ "number": "W9",+ "name": "gpmc_d11",+ "type": "bidirectional",+ "description": "GPMC data bit 11 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_47 in mode 4."+ },+ {+ "number": "AA10",+ "name": "gpmc_d12",+ "type": "bidirectional",+ "description": "GPMC data bit 12 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_48 in mode 4."+ },+ {+ "number": "Y9",+ "name": "gpmc_d13",+ "type": "bidirectional",+ "description": "GPMC data bit 13 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_49 in mode 4."+ },+ {+ "number": "V10",+ "name": "gpmc_d14",+ "type": "bidirectional",+ "description": "GPMC data bit 14 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_50 in mode 4."+ },+ {+ "number": "V9",+ "name": "gpmc_d15",+ "type": "bidirectional",+ "description": "GPMC data bit 15 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_51 in mode 4."+ },+ {+ "number": "Y10",+ "name": "gpmc_ncs0",+ "type": "output",+ "description": "GPMC chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance, no pull."+ },+ {+ "number": "Y11",+ "name": "gpmc_ncs1",+ "type": "output",+ "description": "GPMC chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance; also gpio_52 in mode 4."+ },+ {+ "number": "Y12",+ "name": "gpmc_ncs2",+ "type": "output",+ "description": "GPMC chip select 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpt9_pwm_evt and gpio_53."+ },+ {+ "number": "V12",+ "name": "gpmc_ncs3",+ "type": "output",+ "description": "GPMC chip select 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq0, gpt10_pwm_evt, gpio_54."+ },+ {+ "number": "AA11",+ "name": "gpmc_ncs4",+ "type": "output",+ "description": "GPMC chip select 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq1, gpt9_pwm_evt, gpio_55."+ },+ {+ "number": "W12",+ "name": "gpmc_ncs5",+ "type": "output",+ "description": "GPMC chip select 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq2, gpt10_pwm_evt, gpio_56."+ },+ {+ "number": "AA12",+ "name": "gpmc_ncs6",+ "type": "output",+ "description": "GPMC chip select 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq3, gpt11_pwm_evt, gpio_57."+ },+ {+ "number": "V11",+ "name": "gpmc_ncs7",+ "type": "output",+ "description": "GPMC chip select 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpmc_io_dir, gpt8_pwm_evt, gpio_58."+ },+ {+ "number": "AB13",+ "name": "gpmc_clk",+ "type": "output",+ "description": "GPMC clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_59."+ },+ {+ "number": "AA14",+ "name": "gpmc_nadv_ale",+ "type": "output",+ "description": "GPMC address valid / address latch enable on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance."+ },+ {+ "number": "AB14",+ "name": "gpmc_noe",+ "type": "output",+ "description": "GPMC output enable (active low) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance."+ },+ {+ "number": "AA15",+ "name": "gpmc_nwe",+ "type": "output",+ "description": "GPMC write enable (active low) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance."+ },+ {+ "number": "W11",+ "name": "gpmc_nbe0_cle",+ "type": "output",+ "description": "GPMC byte enable 0 / command latch enable on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_60."+ },+ {+ "number": "Y15",+ "name": "gpmc_nbe1",+ "type": "output",+ "description": "GPMC byte enable 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpio_61."+ },+ {+ "number": "W14",+ "name": "gpmc_nwp",+ "type": "output",+ "description": "GPMC write protect on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_62."+ },+ {+ "number": "V13",+ "name": "gpmc_wait0",+ "type": "input",+ "description": "GPMC wait input 0 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled."+ },+ {+ "number": "AA16",+ "name": "gpmc_wait1",+ "type": "input",+ "description": "GPMC wait input 1 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also uart4_tx and gpio_63."+ },+ {+ "number": "Y14",+ "name": "gpmc_wait2",+ "type": "input",+ "description": "GPMC wait input 2 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also uart4_rx and gpio_64."+ },+ {+ "number": "V14",+ "name": "gpmc_wait3",+ "type": "input",+ "description": "GPMC wait input 3 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also sys_ndmareq1, uart3_ctsn and gpio_65."+ },+ {+ "number": "B22",+ "name": "dss_pclk",+ "type": "output",+ "description": "Display subsystem pixel clock on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup."+ },+ {+ "number": "B21",+ "name": "dss_hsync",+ "type": "output",+ "description": "Display subsystem horizontal sync on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup."+ },+ {+ "number": "B20",+ "name": "dss_vsync",+ "type": "output",+ "description": "Display subsystem vertical sync on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup."+ },+ {+ "number": "B19",+ "name": "dss_acbias",+ "type": "output",+ "description": "Display subsystem AC bias output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "A20",+ "name": "dss_data0",+ "type": "output",+ "description": "Display subsystem data bit 0 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_cts."+ },+ {+ "number": "A19",+ "name": "dss_data1",+ "type": "output",+ "description": "Display subsystem data bit 1 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_rts."+ },+ {+ "number": "A18",+ "name": "dss_data2",+ "type": "output",+ "description": "Display subsystem data bit 2 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "B18",+ "name": "dss_data3",+ "type": "output",+ "description": "Display subsystem data bit 3 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "A17",+ "name": "dss_data4",+ "type": "output",+ "description": "Display subsystem data bit 4 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart3_rx_irrx."+ },+ {+ "number": "C18",+ "name": "dss_data5",+ "type": "output",+ "description": "Display subsystem data bit 5 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart3_tx_irtx."+ },+ {+ "number": "D17",+ "name": "dss_data6",+ "type": "output",+ "description": "Display subsystem data bit 6 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_tx."+ },+ {+ "number": "B16",+ "name": "dss_data7",+ "type": "output",+ "description": "Display subsystem data bit 7 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_rx."+ },+ {+ "number": "B17",+ "name": "dss_data8",+ "type": "output",+ "description": "Display subsystem data bit 8 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C17",+ "name": "dss_data9",+ "type": "output",+ "description": "Display subsystem data bit 9 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C16",+ "name": "dss_data10",+ "type": "output",+ "description": "Display subsystem data bit 10 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "D16",+ "name": "dss_data11",+ "type": "output",+ "description": "Display subsystem data bit 11 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "D14",+ "name": "dss_data12",+ "type": "output",+ "description": "Display subsystem data bit 12 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "A16",+ "name": "dss_data13",+ "type": "output",+ "description": "Display subsystem data bit 13 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "D15",+ "name": "dss_data14",+ "type": "output",+ "description": "Display subsystem data bit 14 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "B15",+ "name": "dss_data15",+ "type": "output",+ "description": "Display subsystem data bit 15 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "A15",+ "name": "dss_data16",+ "type": "output",+ "description": "Display subsystem data bit 16 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "A14",+ "name": "dss_data17",+ "type": "output",+ "description": "Display subsystem data bit 17 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C13",+ "name": "dss_data18",+ "type": "output",+ "description": "Display subsystem data bit 18 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_clk."+ },+ {+ "number": "C15",+ "name": "dss_data19",+ "type": "output",+ "description": "Display subsystem data bit 19 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_simo."+ },+ {+ "number": "A13",+ "name": "dss_data20",+ "type": "output",+ "description": "Display subsystem data bit 20 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_somi."+ },+ {+ "number": "B13",+ "name": "dss_data21",+ "type": "output",+ "description": "Display subsystem data bit 21 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_cs0."+ },+ {+ "number": "C14",+ "name": "dss_data22",+ "type": "output",+ "description": "Display subsystem data bit 22 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_cs1."+ },+ {+ "number": "B14",+ "name": "dss_data23",+ "type": "output",+ "description": "Display subsystem data bit 23 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "AB21",+ "name": "ccdc_pclk",+ "type": "bidirectional",+ "description": "CCDC pixel clock on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg0 and gpio_94."+ },+ {+ "number": "AA21",+ "name": "ccdc_field",+ "type": "bidirectional",+ "description": "CCDC field signal on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also ccdc_data8, uart4_tx and i2c3_scl."+ },+ {+ "number": "Y21",+ "name": "ccdc_hd",+ "type": "bidirectional",+ "description": "CCDC horizontal sync on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also uart4_rts."+ },+ {+ "number": "Y22",+ "name": "ccdc_vd",+ "type": "bidirectional",+ "description": "CCDC vertical sync on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also uart4_cts."+ },+ {+ "number": "W21",+ "name": "ccdc_wen",+ "type": "bidirectional",+ "description": "CCDC write enable on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also ccdc_data9 and uart4_rx."+ },+ {+ "number": "W22",+ "name": "ccdc_data0",+ "type": "input",+ "description": "CCDC data bit 0 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also i2c3_sda."+ },+ {+ "number": "W20",+ "name": "ccdc_data1",+ "type": "input",+ "description": "CCDC data bit 1 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown."+ },+ {+ "number": "V21",+ "name": "ccdc_data2",+ "type": "input",+ "description": "CCDC data bit 2 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg4."+ },+ {+ "number": "V19",+ "name": "ccdc_data3",+ "type": "input",+ "description": "CCDC data bit 3 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg5."+ },+ {+ "number": "V22",+ "name": "ccdc_data4",+ "type": "input",+ "description": "CCDC data bit 4 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg6."+ },+ {+ "number": "U20",+ "name": "ccdc_data5",+ "type": "input",+ "description": "CCDC data bit 5 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg7."+ },+ {+ "number": "V20",+ "name": "ccdc_data6",+ "type": "input",+ "description": "CCDC data bit 6 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown."+ },+ {+ "number": "U19",+ "name": "ccdc_data7",+ "type": "input",+ "description": "CCDC data bit 7 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown."+ },+ {+ "number": "U21",+ "name": "rmii_mdio_data",+ "type": "bidirectional",+ "description": "EMAC RMII management data on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data8 and gpio_107."+ },+ {+ "number": "U22",+ "name": "rmii_mdio_clk",+ "type": "output",+ "description": "EMAC RMII management clock on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data9 and gpio_108."+ },+ {+ "number": "T19",+ "name": "rmii_rxd0",+ "type": "input",+ "description": "EMAC RMII receive data bit 0 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data10."+ },+ {+ "number": "T20",+ "name": "rmii_rxd1",+ "type": "input",+ "description": "EMAC RMII receive data bit 1 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data11."+ },+ {+ "number": "T21",+ "name": "rmii_crs_dv",+ "type": "input",+ "description": "EMAC RMII carrier sense / receive data valid on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup."+ },+ {+ "number": "R22",+ "name": "rmii_rxer",+ "type": "input",+ "description": "EMAC RMII receive error on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data13."+ },+ {+ "number": "T22",+ "name": "rmii_txd0",+ "type": "output",+ "description": "EMAC RMII transmit data bit 0 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup."+ },+ {+ "number": "R20",+ "name": "rmii_txd1",+ "type": "output",+ "description": "EMAC RMII transmit data bit 1 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup."+ },+ {+ "number": "R19",+ "name": "rmii_txen",+ "type": "output",+ "description": "EMAC RMII transmit enable on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup."+ },+ {+ "number": "R21",+ "name": "rmii_50mhz_clk",+ "type": "input",+ "description": "EMAC RMII 50 MHz reference clock input on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup."+ },+ {+ "number": "E5",+ "name": "mcbsp2_fsx",+ "type": "bidirectional",+ "description": "McBSP2 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "D5",+ "name": "mcbsp2_clkx",+ "type": "bidirectional",+ "description": "McBSP2 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C5",+ "name": "mcbsp2_dr",+ "type": "input",+ "description": "McBSP2 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "E4",+ "name": "mcbsp2_dx",+ "type": "bidirectional",+ "description": "McBSP2 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "P22",+ "name": "mmc1_clk",+ "type": "output",+ "description": "MMC1 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "N21",+ "name": "mmc1_cmd",+ "type": "bidirectional",+ "description": "MMC1 command on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "P21",+ "name": "mmc1_dat0",+ "type": "bidirectional",+ "description": "MMC1 data bit 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_clk."+ },+ {+ "number": "N20",+ "name": "mmc1_dat1",+ "type": "bidirectional",+ "description": "MMC1 data bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_simo."+ },+ {+ "number": "P19",+ "name": "mmc1_dat2",+ "type": "bidirectional",+ "description": "MMC1 data bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_somi."+ },+ {+ "number": "P20",+ "name": "mmc1_dat3",+ "type": "bidirectional",+ "description": "MMC1 data bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_cs0."+ },+ {+ "number": "N22",+ "name": "mmc1_dat4",+ "type": "bidirectional",+ "description": "MMC1 data bit 4 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_126."+ },+ {+ "number": "N19",+ "name": "mmc1_dat5",+ "type": "bidirectional",+ "description": "MMC1 data bit 5 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_127."+ },+ {+ "number": "N18",+ "name": "mmc1_dat6",+ "type": "bidirectional",+ "description": "MMC1 data bit 6 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_128."+ },+ {+ "number": "P18",+ "name": "mmc1_dat7",+ "type": "bidirectional",+ "description": "MMC1 data bit 7 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_129."+ },+ {+ "number": "M21",+ "name": "mmc2_clk",+ "type": "output",+ "description": "MMC2 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi3_clk, uart4_cts."+ },+ {+ "number": "M20",+ "name": "mmc2_cmd",+ "type": "bidirectional",+ "description": "MMC2 command on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_simo and uart4_rts."+ },+ {+ "number": "K20",+ "name": "mmc2_dat0",+ "type": "bidirectional",+ "description": "MMC2 data bit 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_somi and uart4_tx."+ },+ {+ "number": "L19",+ "name": "mmc2_dat1",+ "type": "bidirectional",+ "description": "MMC2 data bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also uart4_rx."+ },+ {+ "number": "M18",+ "name": "mmc2_dat2",+ "type": "bidirectional",+ "description": "MMC2 data bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_cs1."+ },+ {+ "number": "K21",+ "name": "mmc2_dat3",+ "type": "bidirectional",+ "description": "MMC2 data bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_cs0."+ },+ {+ "number": "L18",+ "name": "mmc2_dat4",+ "type": "bidirectional",+ "description": "MMC2 data bit 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_data0 and mmc3_dat0."+ },+ {+ "number": "L20",+ "name": "mmc2_dat5",+ "type": "bidirectional",+ "description": "MMC2 data bit 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_data1 and mmc3_dat1."+ },+ {+ "number": "L21",+ "name": "mmc2_dat6",+ "type": "bidirectional",+ "description": "MMC2 data bit 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_cmd and mmc3_dat2."+ },+ {+ "number": "M19",+ "name": "mmc2_dat7",+ "type": "bidirectional",+ "description": "MMC2 data bit 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_clkin and mmc3_dat3."+ },+ {+ "number": "C4",+ "name": "mcbsp3_dx",+ "type": "bidirectional",+ "description": "McBSP3 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_cts."+ },+ {+ "number": "B4",+ "name": "mcbsp3_dr",+ "type": "input",+ "description": "McBSP3 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_rts."+ },+ {+ "number": "D4",+ "name": "mcbsp3_clkx",+ "type": "bidirectional",+ "description": "McBSP3 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_tx."+ },+ {+ "number": "A4",+ "name": "mcbsp3_fsx",+ "type": "bidirectional",+ "description": "McBSP3 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_rx."+ },+ {+ "number": "A5",+ "name": "uart2_cts",+ "type": "input",+ "description": "UART2 clear to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "B5",+ "name": "uart2_rts",+ "type": "output",+ "description": "UART2 request to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "D6",+ "name": "uart2_tx",+ "type": "output",+ "description": "UART2 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "C6",+ "name": "uart2_rx",+ "type": "input",+ "description": "UART2 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "C22",+ "name": "uart1_tx",+ "type": "output",+ "description": "UART1 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C21",+ "name": "uart1_rts",+ "type": "output",+ "description": "UART1 request to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C19",+ "name": "uart1_cts",+ "type": "input",+ "description": "UART1 clear to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C20",+ "name": "uart1_rx",+ "type": "input",+ "description": "UART1 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcbsp1_clkr and mcspi4_clk."+ },+ {+ "number": "A3",+ "name": "mcbsp4_clkx",+ "type": "bidirectional",+ "description": "McBSP4 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txse0."+ },+ {+ "number": "B3",+ "name": "mcbsp4_dr",+ "type": "input",+ "description": "McBSP4 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_rxrcv."+ },+ {+ "number": "A2",+ "name": "mcbsp4_dx",+ "type": "bidirectional",+ "description": "McBSP4 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txdat."+ },+ {+ "number": "B2",+ "name": "mcbsp4_fsx",+ "type": "bidirectional",+ "description": "McBSP4 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txen_n."+ },+ {+ "number": "B11",+ "name": "mcbsp1_clkr",+ "type": "bidirectional",+ "description": "McBSP1 receive clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_clk."+ },+ {+ "number": "D11",+ "name": "mcbsp1_fsr",+ "type": "bidirectional",+ "description": "McBSP1 frame sync receive on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C10",+ "name": "mcbsp1_dx",+ "type": "bidirectional",+ "description": "McBSP1 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_simo and mcbsp3_dx."+ },+ {+ "number": "C9",+ "name": "mcbsp1_dr",+ "type": "input",+ "description": "McBSP1 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_somi and mcbsp3_dr."+ },+ {+ "number": "E11",+ "name": "mcbsp_clks",+ "type": "input",+ "description": "McBSP sample rate clock input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart1_cts."+ },+ {+ "number": "C11",+ "name": "mcbsp1_fsx",+ "type": "bidirectional",+ "description": "McBSP1 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_cs0 and mcbsp3_fsx."+ },+ {+ "number": "C8",+ "name": "mcbsp1_clkx",+ "type": "bidirectional",+ "description": "McBSP1 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcbsp3_clkx."+ },+ {+ "number": "W15",+ "name": "uart3_cts_rctx",+ "type": "bidirectional",+ "description": "UART3 clear to send (input) / remote TX (output) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "W13",+ "name": "uart3_rts_sd",+ "type": "output",+ "description": "UART3 request to send / IR enable output on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "AA13",+ "name": "uart3_rx_irrx",+ "type": "input",+ "description": "UART3 receive data / IR and remote RX input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "Y13",+ "name": "uart3_tx_irtx",+ "type": "output",+ "description": "UART3 transmit data / IR TX output on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup."+ },+ {+ "number": "A6",+ "name": "usb0_dp",+ "type": "bidirectional",+ "description": "USB0 D+ differential signal pair, 5.0 V tolerant, with internal PU/PD."+ },+ {+ "number": "B6",+ "name": "usb0_dm",+ "type": "bidirectional",+ "description": "USB0 D- differential signal pair, 5.0 V tolerant, with internal PU/PD."+ },+ {+ "number": "C7",+ "name": "usb0_vbus",+ "type": "passive",+ "description": "USB0 VBUS analog input; tie to USB connector (host/device) or external charge pump and VBUS (OTG), VDDA3P3V_USBPHY 3.3 V."+ },+ {+ "number": "B7",+ "name": "usb0_id",+ "type": "passive",+ "description": "USB0 operating mode identification (analog) pin on VDDA3P3V_USBPHY (3.3 V)."+ },+ {+ "number": "A7",+ "name": "usb0_drvvbus",+ "type": "output",+ "description": "Digital output controlling external VBUS supply on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart3_tx_irtx and gpio_125."+ },+ {+ "number": "AB15",+ "name": "hecc1_txd",+ "type": "output",+ "description": "HECC1 CAN transmit on VDDSHV (1.8 V/3.3 V), 24 pF load, reset state 1 with pullup; also uart3_rx_irrx and gpio_130."+ },+ {+ "number": "AB16",+ "name": "hecc1_rxd",+ "type": "input",+ "description": "HECC1 CAN receive on VDDSHV (1.8 V/3.3 V), 24 pF load, reset state 1 with pullup; also uart3_rts_sd and gpio_131."+ },+ {+ "number": "AA17",+ "name": "i2c1_scl",+ "type": "bidirectional",+ "description": "I2C1 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup."+ },+ {+ "number": "AB17",+ "name": "i2c1_sda",+ "type": "bidirectional",+ "description": "I2C1 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup."+ },+ {+ "number": "Y17",+ "name": "i2c2_scl",+ "type": "bidirectional",+ "description": "I2C2 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_168."+ },+ {+ "number": "Y16",+ "name": "i2c2_sda",+ "type": "bidirectional",+ "description": "I2C2 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_183."+ },+ {+ "number": "W16",+ "name": "i2c3_scl",+ "type": "bidirectional",+ "description": "I2C3 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_184."+ },+ {+ "number": "W17",+ "name": "i2c3_sda",+ "type": "bidirectional",+ "description": "I2C3 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_185."+ },+ {+ "number": "B9",+ "name": "hdq_sio",+ "type": "bidirectional",+ "description": "HDQ/1-Wire single-wire data on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup."+ },+ {+ "number": "K22",+ "name": "mcspi1_clk",+ "type": "bidirectional",+ "description": "McSPI1 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat4."+ },+ {+ "number": "K19",+ "name": "mcspi1_simo",+ "type": "bidirectional",+ "description": "McSPI1 SIMO on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat5."+ },+ {+ "number": "J18",+ "name": "mcspi1_somi",+ "type": "bidirectional",+ "description": "McSPI1 SOMI on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat6."+ },+ {+ "number": "K18",+ "name": "mcspi1_cs0",+ "type": "bidirectional",+ "description": "McSPI1 chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc2_dat7."+ },+ {+ "number": "J20",+ "name": "mcspi1_cs1",+ "type": "output",+ "description": "McSPI1 chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc3_cmd."+ },+ {+ "number": "J19",+ "name": "mcspi1_cs2",+ "type": "output",+ "description": "McSPI1 chip select 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc3_clk."+ },+ {+ "number": "J21",+ "name": "mcspi1_cs3",+ "type": "output",+ "description": "McSPI1 chip select 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also hsusb2_data2 and mm_fsusb2_txdat."+ },+ {+ "number": "J22",+ "name": "mcspi2_clk",+ "type": "bidirectional",+ "description": "McSPI2 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also hsusb2_data7."+ },+ {+ "number": "H20",+ "name": "mcspi2_simo",+ "type": "bidirectional",+ "description": "McSPI2 SIMO on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt9_pwm_evt and hsusb2_data4."+ },+ {+ "number": "H22",+ "name": "mcspi2_somi",+ "type": "bidirectional",+ "description": "McSPI2 SOMI on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt10_pwm_evt and hsusb2_data5."+ },+ {+ "number": "H21",+ "name": "mcspi2_cs0",+ "type": "bidirectional",+ "description": "McSPI2 chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpt11_pwm_evt and hsusb2_data6."+ },+ {+ "number": "H19",+ "name": "mcspi2_cs1",+ "type": "output",+ "description": "McSPI2 chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt8_pwm_evt and hsusb2_data3."+ },+ {+ "number": "A8",+ "name": "sys_32k",+ "type": "input",+ "description": "32 kHz clock input on VDDSHV (1.8 V/3.3 V), 30 pF load, high-impedance at reset."+ },+ {+ "number": "A10",+ "name": "sys_xtalin",+ "type": "input",+ "description": "Oscillator crystal input on VDDSOSC (1.8 V), high-impedance at reset."+ },+ {+ "number": "A9",+ "name": "sys_xtalout",+ "type": "output",+ "description": "Oscillator crystal output on VDDSOSC (1.8 V), high-impedance at reset."+ },+ {+ "number": "B8",+ "name": "sys_clkreq",+ "type": "bidirectional",+ "description": "System clock request on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_1."+ },+ {+ "number": "AB18",+ "name": "sys_nirq",+ "type": "input",+ "description": "System interrupt input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpio_0."+ },+ {+ "number": "AA18",+ "name": "sys_nrespwron",+ "type": "input",+ "description": "Power-on reset input on VDDSHV (1.8 V/3.3 V), high-impedance at reset."+ },+ {+ "number": "Y18",+ "name": "sys_nreswarm",+ "type": "bidirectional",+ "description": "Warm reset bidirectional on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; open-drain function on gpio_30."+ },+ {+ "number": "AB19",+ "name": "sys_boot0",+ "type": "input",+ "description": "Boot configuration input 0 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_2."+ },+ {+ "number": "AB20",+ "name": "sys_boot1",+ "type": "input",+ "description": "Boot configuration input 1 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_3."+ },+ {+ "number": "W18",+ "name": "sys_boot2",+ "type": "input",+ "description": "Boot configuration input 2 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_4."+ },+ {+ "number": "AA19",+ "name": "sys_boot3",+ "type": "input",+ "description": "Boot configuration input 3 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_5."+ },+ {+ "number": "V18",+ "name": "sys_boot4",+ "type": "input",+ "description": "Boot configuration input 4 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also mmc2_dir_data2 and gpio_6."+ },+ {+ "number": "Y19",+ "name": "sys_boot5",+ "type": "input",+ "description": "Boot configuration input 5 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also mmc2_dir_data3 and gpio_7."+ },+ {+ "number": "W19",+ "name": "sys_boot6",+ "type": "input",+ "description": "Boot configuration input 6 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_8."+ },+ {+ "number": "AA20",+ "name": "sys_boot7",+ "type": "input",+ "description": "Boot configuration input 7 on VDDSHV (1.8 V/3.3 V), high-impedance at reset with pullup."+ },+ {+ "number": "Y20",+ "name": "sys_boot8",+ "type": "input",+ "description": "Boot configuration input 8 on VDDSHV (1.8 V/3.3 V), high-impedance at reset with pullup."+ },+ {+ "number": "E9",+ "name": "sys_clkout1",+ "type": "output",+ "description": "System clock output 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pulldown; mux 0 if sys_boot6 is pulled down (clock master); also gpio_10."+ },+ {+ "number": "E10",+ "name": "sys_clkout2",+ "type": "output",+ "description": "System clock output 2 on VDDSHV (1.8 V/3.3 V), 10 pF load, reset state 0 with pulldown; also gpio_186."+ },+ {+ "number": "D13",+ "name": "jtag_ntrst",+ "type": "input",+ "description": "JTAG test reset input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "E14",+ "name": "jtag_tck",+ "type": "input",+ "description": "JTAG test clock input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown."+ },+ {+ "number": "C12",+ "name": "jtag_rtck",+ "type": "output",+ "description": "JTAG return test clock output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 high-impedance."+ },+ {+ "number": "A12",+ "name": "jtag_tms_tmsc",+ "type": "bidirectional",+ "description": "JTAG test mode select / TMSC on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup."+ },+ {+ "number": "B12",+ "name": "jtag_tdi",+ "type": "input",+ "description": "JTAG test data input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup."+ },+ {+ "number": "D12",+ "name": "jtag_tdo",+ "type": "output",+ "description": "JTAG test data output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 high-impedance."+ },+ {+ "number": "E13",+ "name": "jtag_emu0",+ "type": "bidirectional",+ "description": "JTAG emulation pin 0 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup; also gpio_11."+ },+ {+ "number": "E12",+ "name": "jtag_emu1",+ "type": "bidirectional",+ "description": "JTAG emulation pin 1 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup; also gpio_31."+ },+ {+ "number": "G22",+ "name": "etk_clk",+ "type": "output",+ "description": "ETK trace clock on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcbsp5_clkx, mmc3_clk, hsusb1_stp and gpio_12."+ },+ {+ "number": "G21",+ "name": "etk_ctl",+ "type": "output",+ "description": "ETK trace control on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mmc3_cmd, hsusb1_clk and gpio_13."+ },+ {+ "number": "G20",+ "name": "etk_d0",+ "type": "output",+ "description": "ETK trace data bit 0 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_simo and hsusb1_data0."+ },+ {+ "number": "F22",+ "name": "etk_d1",+ "type": "output",+ "description": "ETK trace data bit 1 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_somi and hsusb1_data1."+ },+ {+ "number": "F20",+ "name": "etk_d2",+ "type": "output",+ "description": "ETK trace data bit 2 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_cs0 and hsusb1_data2."+ },+ {+ "number": "G19",+ "name": "etk_d3",+ "type": "output",+ "description": "ETK trace data bit 3 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pullup; also mcspi3_clk and hsusb1_data7."+ },+ {+ "number": "E19",+ "name": "etk_d4",+ "type": "output",+ "description": "ETK trace data bit 4 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_dr and hsusb1_data4."+ },+ {+ "number": "F21",+ "name": "etk_d5",+ "type": "output",+ "description": "ETK trace data bit 5 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_fsx and hsusb1_data5."+ },+ {+ "number": "F19",+ "name": "etk_d6",+ "type": "output",+ "description": "ETK trace data bit 6 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_dx and hsusb1_data6."+ },+ {+ "number": "E21",+ "name": "etk_d7",+ "type": "output",+ "description": "ETK trace data bit 7 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcspi3_cs1 and hsusb1_data3."+ },+ {+ "number": "D22",+ "name": "etk_d8",+ "type": "output",+ "description": "ETK trace data bit 8 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mmc3_dat6 and hsusb1_dir."+ },+ {+ "number": "D21",+ "name": "etk_d9",+ "type": "output",+ "description": "ETK trace data bit 9 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mmc3_dat5 and hsusb1_nxt."+ },+ {+ "number": "E22",+ "name": "etk_d10",+ "type": "output",+ "description": "ETK trace data bit 10 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also uart1_rx and hsusb2_clk."+ },+ {+ "number": "E20",+ "name": "etk_d11",+ "type": "output",+ "description": "ETK trace data bit 11 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcspi3_clk and hsusb2_stp."+ },+ {+ "number": "E18",+ "name": "etk_d12",+ "type": "output",+ "description": "ETK trace data bit 12 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_dir."+ },+ {+ "number": "D20",+ "name": "etk_d13",+ "type": "output",+ "description": "ETK trace data bit 13 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_nxt."+ },+ {+ "number": "D19",+ "name": "etk_d14",+ "type": "output",+ "description": "ETK trace data bit 14 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_data0."+ },+ {+ "number": "D18",+ "name": "etk_d15",+ "type": "output",+ "description": "ETK trace data bit 15 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_data1."+ },+ {+ "number": "M2",+ "name": "ddr_padref",+ "type": "passive",+ "description": "DDR pad reference voltage on VDDS (1.8 V)."+ },+ {+ "number": "J8",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "J10",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "J12",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "J14",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "J16",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "K9",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "K11",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "K13",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "K15",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "L8",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "L10",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "L12",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "L14",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "M7",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "M9",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "M11",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "M13",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "M15",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "N8",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "N10",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "N12",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "N14",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "P7",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "P9",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "P11",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "P13",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "P15",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "R8",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "R10",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "R12",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "R14",+ "name": "VDD_CORE",+ "type": "power_in",+ "description": "Core logic supply, 1.2 V nominal."+ },+ {+ "number": "L17",+ "name": "VDDS_SRAM_MPU",+ "type": "power_in",+ "description": "SRAM supply for the MPU domain, 1.8 V."+ },+ {+ "number": "J6",+ "name": "VDDS_SRAM_CORE_BG",+ "type": "power_in",+ "description": "SRAM supply for the core domain (bandgap), 1.8 V."+ },+ {+ "number": "M17",+ "name": "CAP_VDD_SRAM_MPU",+ "type": "power_in",+ "description": "SRAM core voltage capacitor node for the MPU domain, 1.2 V."+ },+ {+ "number": "K6",+ "name": "CAP_VDD_SRAM_CORE",+ "type": "power_in",+ "description": "SRAM core voltage capacitor node for the core domain, 1.2 V."+ },+ {+ "number": "K17",+ "name": "VDDS_DPLL_MPU_USBHOST",+ "type": "power_in",+ "description": "DPLL supply for MPU and USB host clocks, 1.8 V; requires the noise filter in Table 5-19."+ },+ {+ "number": "F11",+ "name": "VDDS_DPLL_PER_CORE",+ "type": "power_in",+ "description": "DPLL supply for peripheral and core clocks, 1.8 V; requires the noise filter in Table 5-19."+ },+ {+ "number": "F7",+ "name": "VDDA3P3V_USBPHY",+ "type": "power_in",+ "description": "USB PHY analog supply, 3.3 V."+ },+ {+ "number": "D7",+ "name": "VDDA1P8V_USBPHY",+ "type": "power_in",+ "description": "USB PHY analog supply, 1.8 V."+ },+ {+ "number": "E7",+ "name": "CAP_VDDA1_P2LDO_USBPHY",+ "type": "passive",+ "description": "USB PHY internal LDO capacitor node, 1.2 V (printed name wraps across lines)."+ },+ {+ "number": "A21",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "B1",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "E15",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "E17",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "F12",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "F14",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "F18",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "G10",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "G12",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "G13",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "G8",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "G17",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "H18",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "J17",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "L22",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "N16",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "P17",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "R16",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "R18",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "T9",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "T11",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "T13",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "T17",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "U8",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "U10",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "U12",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "U14",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "U16",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "U18",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "V7",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "V8",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "V17",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "AA22",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "AB11",+ "name": "VDDSHV",+ "type": "power_in",+ "description": "I/O supply for 1.8 V/3.3 V peripheral buffers."+ },+ {+ "number": "F5",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "F16",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "G15",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "H5",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "K7",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "L6",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "L16",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "N1",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "N5",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "N6",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "P5",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "R6",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "T5",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "T7",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "T15",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "U6",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "AA1",+ "name": "VDDS",+ "type": "power_in",+ "description": "I/O supply for DDR2/mDDR interface buffers, 1.8 V."+ },+ {+ "number": "L5",+ "name": "VREFSSTL",+ "type": "input",+ "description": "DDR SSTL reference voltage input, 0.5 × VDDS."+ },+ {+ "number": "G9",+ "name": "VDDSOSC",+ "type": "power_in",+ "description": "Oscillator supply, 1.8 V."+ },+ {+ "number": "B10",+ "name": "VSSOSC",+ "type": "power_in",+ "description": "Oscillator ground."+ },+ {+ "number": "A1",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "A11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "A22",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "E6",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "E16",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "F6",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "F13",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "F15",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "F17",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G5",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G14",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G16",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {