aip8563sa8-tr

@@ -33,5 +33,78 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "AIP8563SA8.TR",+    "manufacturer": "Wuxi I core Elec AIP8563SA8 TR",+    "package": "SOP-8",+    "pin_count": 8,+    "category": "Real-time Clocks (RTC)",+    "parts": {+      "symbol": "aip8563sa8-tr.kicad_sym",+      "footprint": "aip8563sa8-tr.kicad_mod",+      "model_3d": "aip8563sa8-tr-etched.glb",+      "model_3d_plain": "aip8563sa8-tr.glb",+      "model_3d_step": "aip8563sa8-tr-etched.step",+      "model_3d_step_plain": "aip8563sa8-tr.step",+      "lbr": "aip8563sa8-tr.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "OSCI",+        "type": "input",+        "description": "32.768 kHz crystal oscillator input. Connect to one terminal of a 32.768 kHz quartz crystal; internal oscillator capacitors are integrated but an external trim cap (5-25 pF) may be used for frequency adjustment. Absolute-max input voltage -0.5 V to VDD+0.5 V."+      },+      {+        "number": "2",+        "name": "OSCO",+        "type": "output",+        "description": "32.768 kHz crystal oscillator output. Connect to the other terminal of the 32.768 kHz quartz crystal. Do not load externally beyond the crystal network."+      },+      {+        "number": "3",+        "name": "/INT",+        "type": "output",+        "description": "Interrupt output, active LOW, open-drain. Asserted by the alarm flag (AF) and/or timer flag (TF) per the AIE/TIE and TI/TP settings in control/status register 2. Requires an external pull-up resistor to V1/VDD; leave floating or tie to VDD via pull-up if unused."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground / negative supply reference (0 V)."+      },+      {+        "number": "5",+        "name": "SDA",+        "type": "bidirectional",+        "description": "I2C serial data I/O (open-drain). Requires an external pull-up resistor (R = tr/Cb) to V1/VDD. Supports up to 400 kHz bus rate over VDD = 1.8-5.5 V; VIL ≤ 0.3·VDD, VIH ≥ 0.7·VDD."+      },+      {+        "number": "6",+        "name": "SCL",+        "type": "input",+        "description": "I2C serial clock input (open-drain, requires external pull-up to V1/VDD). Max clock frequency 400 kHz; VIL ≤ 0.3·VDD, VIH ≥ 0.7·VDD. In EXT_CLK test mode the SCL role is separate from CLKOUT which becomes the test-clock input."+      },+      {+        "number": "7",+        "name": "CLKOUT",+        "type": "output",+        "description": "Programmable clock output (open-drain). Selectable frequency 32.768 kHz (default), 1024 Hz, 32 Hz, or 1 Hz via the CLKOUT frequency register (0Dh). High-impedance when FE=0. In EXT_CLK test mode (TEST1=1) this pin becomes an input for an external 64 Hz test clock."+      },+      {+        "number": "8",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. Operating range 1.8 V to 5.5 V for I2C-active operation (down to ~1.0 V for data retention with I2C inactive). Absolute max 6.5 V. Typical sleep current 0.25 uA at VDD=3.0 V, Tamb=25°C."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}