component
ADUM163N1BRZ-RL7
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Analog Devices Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+124adum163n1brz-rl7-etched.glbadum163n1brz-rl7-hero.glbadum163n1brz-rl7-hero.overlay.json+436adum163n1brz-rl7.glbadum163n1brz-rl7.kicad_mod+348adum163n1brz-rl7.kicad_sym+77adum163n1brz-rl7.lbr+154adum163n1brz-rl7.step+10625docs/adum163n1brz-rl7-datasheet.pdfdocs/hero.pngpackage.json+242page.json+248viewers/footprint.html+1viewers/symbol.html+1README.mdadded+124@@ -0,0 +1,124 @@+# ADUM163N1BRZ-RL7++**Analog Devices** · Digital Isolators · SOIC-16++ADUM163N1BRZ-RL7 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 1.7 V to 5.5 V in the recommended operating conditions. |+| 2 | VIA | input | Logic Input A; when the side 1 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry. |+| 3 | VIB | input | Logic Input B; when the side 1 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry. |+| 4 | VIC | input | Logic Input C; when the side 1 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry. |+| 5 | VOD | output | Logic Output D; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered. |+| 6 | VOE | output | Logic Output E; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered. |+| 7 | VOF | output | Logic Output F; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered. |+| 8 | GND1 | power_in | Ground 1; ground reference for isolator side 1. |+| 9 | GND2 | power_in | Ground 2; ground reference for isolator side 2. |+| 10 | VIF | input | Logic Input F; when the side 2 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry. |+| 11 | VIE | input | Logic Input E; when the side 2 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry. |+| 12 | VID | input | Logic Input D; when the side 2 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry. |+| 13 | VOC | output | Logic Output C; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered. |+| 14 | VOB | output | Logic Output B; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered. |+| 15 | VOA | output | Logic Output A; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered. |+| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 1.7 V to 5.5 V in the recommended operating conditions. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | SOIC-16 |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 16 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Operating Temperature | TA | -40 | | 125 | °C | | 14 |+| Supply Voltages | VDD1, VDD2 | 1.7 | | 5.5 | V | | 14 |+| Input Signal Rise and Fall Times | | | | 1 | ms | Printed as Rating 1.0 ms with no min/max qualifier | 14 |+| Storage Temperature Range | TST | -65 | | 150 | °C | | 15 |+| Ambient Operating Temperature Range | TA | -40 | | 125 | °C | | 15 |+| Supply Voltages | VDD1, VDD2 | -0.5 | | 7 | V | | 15 |+| Input Voltages | VIA, VIB, VIC, VID, VIE, VIF | -0.5 | | | V | Maximum printed as VDDI1 + 0.5 V (not numeric) | 15 |+| Output Voltages | VOA, VOB, VOC, VOD, VOE, VOF | -0.5 | | | V | Maximum printed as VDDO2 + 0.5 V (not numeric) | 15 |+| Side 1 Average Output Current per Pin | IO1 | -10 | | 10 | mA | Average output current per pin | 15 |+| Side 2 Average Output Current per Pin | IO2 | -10 | | 10 | mA | Average output current per pin | 15 |+| Common-Mode Transients | | -150 | | 150 | kV/µs | Across the insulation barrier | 15 |+| Pulse Width | PW | 6.6 | | | ns | Within pulse width distortion (PWD) limit; all voltages | 4 |+| Data Rate | | 150 | | | Mbps | Within PWD limit; all voltages | 4 |+| Common-Mode Transient Immunity /CMH/ | /CMH/ | 75 | 100 | | kV/µs | VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V; all voltages | 4 |+| Common-Mode Transient Immunity /CML/ | /CML/ | 75 | 100 | | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V; all voltages | 4 |+| Input Current per Channel | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx; all voltages | 4 |+| Propagation Delay tPHL, tPLH (5 V operation) | tPHL, tPLH | 4.8 | 7.2 | 13 | ns | 50% input to 50% output | 4 |+| Pulse Width Distortion (5 V operation) | PWD | | 0.5 | 4.5 | ns | /tPLH − tPHL/ | 4 |+| Channel Matching Codirectional (5 V operation) | tPSKCD | | 0.5 | 4 | ns | | 4 |+| Channel Matching Opposing Direction (5 V operation) | tPSKOD | | 0.5 | 4.5 | ns | | 4 |+| Logic Low Output Voltage (5 V operation) | VOL | | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 4 |+| Logic Low Output Voltage (5 V operation) | VOL | | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 4 |+| Quiescent Supply Current Side 1 (5 V operation) | IDD1 (Q) | | 3 | 4.26 | mA | VI5 = 0 (N0), 1 (N1) | 4 |+| Quiescent Supply Current Side 2 (5 V operation) | IDD2 (Q) | | 2.8 | 3.92 | mA | VI5 = 0 (N0), 1 (N1) | 4 |+| Quiescent Supply Current Side 1 (5 V operation) | IDD1 (Q) | | 11.8 | 18.9 | mA | VI5 = 1 (N0), 0 (N1) | 4 |+| Quiescent Supply Current Side 2 (5 V operation) | IDD2 (Q) | | 14.6 | 23 | mA | VI5 = 1 (N0), 0 (N1) | 5 |+| Propagation Delay tPHL, tPLH (3.3 V operation) | tPHL, tPLH | 4.8 | 6.8 | 14 | ns | 50% input to 50% output | 6 |+| Pulse Width Distortion (3.3 V operation) | PWD | | 0.7 | 4.5 | ns | /tPLH − tPHL/ | 6 |+| Channel Matching Codirectional (3.3 V operation) | tPSKCD | | 0.7 | 4 | ns | | 6 |+| Channel Matching Opposing Direction (3.3 V operation) | tPSKOD | | 0.7 | 4.5 | ns | | 6 |+| Logic Low Output Voltage (3.3 V operation) | VOL | | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 6 |+| Logic Low Output Voltage (3.3 V operation) | VOL | | 0.2 | 0.4 | V | IOx = 2 mA, VIx = VIxL | 6 |+| Quiescent Supply Current Side 1 (3.3 V operation) | IDD1 (Q) | | 2.8 | 4.16 | mA | VI5 = 0 (N0), 1 (N1) | 6 |+| Quiescent Supply Current Side 2 (3.3 V operation) | IDD2 (Q) | | 2.6 | 3.82 | mA | VI5 = 0 (N0), 1 (N1) | 6 |+| Quiescent Supply Current Side 1 (3.3 V operation) | IDD1 (Q) | | 11.5 | 18.5 | mA | VI5 = 1 (N0), 0 (N1) | 6 |+| Quiescent Supply Current Side 2 (3.3 V operation) | IDD2 (Q) | | 14.3 | 22.5 | mA | VI5 = 1 (N0), 0 (N1) | 7 |+| Propagation Delay tPHL, tPLH (2.5 V operation) | tPHL, tPLH | 5 | 7 | 14 | ns | 50% input to 50% output | 8 |+| Pulse Width Distortion (2.5 V operation) | PWD | | 0.7 | 5 | ns | /tPLH − tPHL/ | 8 |+| Channel Matching Codirectional (2.5 V operation) | tPSKCD | | 0.7 | 5 | ns | | 8 |+| Channel Matching Opposing Direction (2.5 V operation) | tPSKOD | | 0.7 | 5 | ns | | 8 |+| Logic Low Output Voltage (2.5 V operation) | VOL | | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 8 |+| Logic Low Output Voltage (2.5 V operation) | VOL | | 0.2 | 0.4 | V | IOx = 2 mA, VIx = VIxL | 8 |+| Quiescent Supply Current Side 1 (2.5 V operation) | IDD1 (Q) | | 2.7 | 4.08 | mA | VI5 = 0 (N0), 1 (N1) | 8 |+| Quiescent Supply Current Side 2 (2.5 V operation) | IDD2 (Q) | | 2.55 | 3.72 | mA | VI5 = 0 (N0), 1 (N1) | 8 |+| Quiescent Supply Current Side 1 (2.5 V operation) | IDD1 (Q) | | 11.5 | 18.4 | mA | VI5 = 1 (N0), 0 (N1) | 8 |+| Quiescent Supply Current Side 2 (2.5 V operation) | IDD2 (Q) | | 14.3 | 22.3 | mA | VI5 = 1 (N0), 0 (N1) | 9 |+| Propagation Delay tPHL, tPLH (1.8 V operation) | tPHL, tPLH | 5.8 | 8.7 | 15 | ns | 50% input to 50% output | 10 |+| Pulse Width Distortion (1.8 V operation) | PWD | | 0.7 | 5 | ns | /tPLH − tPHL/ | 10 |+| Channel Matching Codirectional (1.8 V operation) | tPSKCD | | 0.7 | 5 | ns | | 10 |+| Channel Matching Opposing Direction (1.8 V operation) | tPSKOD | | 0.7 | 5 | ns | | 10 |+| Logic Low Output Voltage (1.8 V operation) | VOL | | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 10 |+| Logic Low Output Voltage (1.8 V operation) | VOL | | 0.2 | 0.4 | V | IOx = 2 mA, VIx = VIxL | 10 |+| Quiescent Supply Current Side 1 (1.8 V operation) | IDD1 (Q) | | 2.6 | 4.03 | mA | VI5 = 0 (N0), 1 (N1) | 10 |+| Quiescent Supply Current Side 2 (1.8 V operation) | IDD2 (Q) | | 2.5 | 3.72 | mA | VI5 = 0 (N0), 1 (N1) | 10 |+| Quiescent Supply Current Side 1 (1.8 V operation) | IDD1 (Q) | | 11.3 | 18.3 | mA | VI5 = 1 (N0), 0 (N1) | 10 |+| Quiescent Supply Current Side 2 (1.8 V operation) | IDD2 (Q) | | 14 | 22 | mA | VI5 = 1 (N0), 0 (N1) | 11 |+| IC Junction to Ambient Thermal Resistance | θJA | | 75 | | °C/W | Thermocouple located at center of package underside | 12 |++## Materials and finish++As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).++| Part | Material | Colour / plating | Datasheet says | Page |+|---|---|---|---|---|+| housing | pC | | In accordance with DIN EN IEC 60747 (VDE 0884-17) each ADuM160N/ADuM161N/ADuM162N/ADuM163N in the R-16, narrow-body (SOIC_N) package is proof tested by applying an insulation test voltage ≥ 1059 V pea | 13 |++## CAD (KiCad official)++- Symbol: `ADUM163N1BRZ-RL7`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `adum163n1brz-rl7-etched.step` / `adum163n1brz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum163n1brz-rl7.step` / `adum163n1brz-rl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM160N-161N-162N-163N.pdf) (25 pp, sha256 `716242daccaa34f4`, retrieved 2026-10-31, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adum163n1brz-rl7-datasheet.pdf)
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adum163n1brz-rl7.kicad_symadded+77@@ -0,0 +1,77 @@+(kicad_symbol_lib (version 20211014) (generator ds2sf_rect)+ (symbol "ADUM163N1BRZ-RL7" (in_bom yes) (on_board yes)+ (property "Reference" "U" (at 0 12.70 0) (effects (font (size 1.27 1.27))))+ (property "Value" "ADUM163N1BRZ-RL7" (at 0 -15.24 0) (effects (font (size 1.27 1.27))))+ (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))+ (symbol "ADUM163N1BRZ-RL7_0_1"+ (rectangle (start -12.70 10.16) (end 12.70 -12.70)+ (stroke (width 0.254) (type default)) (fill (type background)))+ )+ (symbol "ADUM163N1BRZ-RL7_1_1"+ (pin power_in line (at -17.78 7.62 0) (length 5.08)+ (name "VDD1" (effects (font (size 1.27 1.27))))+ (number "1" (effects (font (size 1.27 1.27))))+ )+ (pin input line (at -17.78 5.08 0) (length 5.08)+ (name "VIA" (effects (font (size 1.27 1.27))))+ (number "2" (effects (font (size 1.27 1.27))))+ )+ (pin input line (at -17.78 2.54 0) (length 5.08)+ (name "VIB" (effects (font (size 1.27 1.27))))+ (number "3" (effects (font (size 1.27 1.27))))+ )+ (pin input line (at -17.78 0.00 0) (length 5.08)+ (name "VIC" (effects (font (size 1.27 1.27))))+ (number "4" (effects (font (size 1.27 1.27))))+ )+ (pin output line (at -17.78 -2.54 0) (length 5.08)+ (name "VOD" (effects (font (size 1.27 1.27))))+ (number "5" (effects (font (size 1.27 1.27))))+ )+ (pin output line (at -17.78 -5.08 0) (length 5.08)+ (name "VOE" (effects (font (size 1.27 1.27))))+ (number "6" (effects (font (size 1.27 1.27))))+ )+ (pin output line (at -17.78 -7.62 0) (length 5.08)+ (name "VOF" (effects (font (size 1.27 1.27))))+ (number "7" (effects (font (size 1.27 1.27))))+ )+ (pin power_in line (at -17.78 -10.16 0) (length 5.08)+ (name "GND1" (effects (font (size 1.27 1.27))))+ (number "8" (effects (font (size 1.27 1.27))))+ )+ (pin power_in line (at 17.78 7.62 180) (length 5.08)+ (name "VDD2" (effects (font (size 1.27 1.27))))+ (number "16" (effects (font (size 1.27 1.27))))+ )+ (pin output line (at 17.78 5.08 180) (length 5.08)+ (name "VOA" (effects (font (size 1.27 1.27))))+ (number "15" (effects (font (size 1.27 1.27))))+ )+ (pin output line (at 17.78 2.54 180) (length 5.08)+ (name "VOB" (effects (font (size 1.27 1.27))))+ (number "14" (effects (font (size 1.27 1.27))))+ )+ (pin output line (at 17.78 0.00 180) (length 5.08)+ (name "VOC" (effects (font (size 1.27 1.27))))+ (number "13" (effects (font (size 1.27 1.27))))+ )+ (pin input line (at 17.78 -2.54 180) (length 5.08)+ (name "VID" (effects (font (size 1.27 1.27))))+ (number "12" (effects (font (size 1.27 1.27))))+ )+ (pin input line (at 17.78 -5.08 180) (length 5.08)+ (name "VIE" (effects (font (size 1.27 1.27))))+ (number "11" (effects (font (size 1.27 1.27))))+ )+ (pin input line (at 17.78 -7.62 180) (length 5.08)+ (name "VIF" (effects (font (size 1.27 1.27))))+ (number "10" (effects (font (size 1.27 1.27))))+ )+ (pin power_in line (at 17.78 -10.16 180) (length 5.08)+ (name "GND2" (effects (font (size 1.27 1.27))))+ (number "9" (effects (font (size 1.27 1.27))))+ )+ )+ )+)
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9.9 mm, 1.27 mm pitch</description>+ <smd name="1" x="-2.4750" y="4.4450" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="2" x="-2.4750" y="3.1750" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="3" x="-2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="4" x="-2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="5" x="-2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="6" x="-2.4750" y="-1.9050" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="7" x="-2.4750" y="-3.1750" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="8" x="-2.4750" y="-4.4450" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="9" x="2.4750" y="-4.4450" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="10" x="2.4750" y="-3.1750" dx="1.9500" dy="0.6000" layer="1" roundness="50"/>+ <smd name="11" x="2.4750" y="-1.9050" dx="1.9500" dy="0.6000" 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direction="in" rot="R180"/>+ <pin name="VIE" x="17.78" y="-5.08" length="middle" direction="in" rot="R180"/>+ <pin name="VIF" x="17.78" y="-7.62" length="middle" direction="in" rot="R180"/>+ <pin name="GND2" x="17.78" y="-10.16" length="middle" direction="pwr" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="ADUM163N1BRZ-RL7" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="ADUM163N1BRZ-RL7" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="SOIC-16_3.9x9.9mm_P1.27mm">+ <connects>+ <connect gate="G$1" pin="VDD1" pad="1"/>+ <connect gate="G$1" pin="VIA" pad="2"/>+ <connect gate="G$1" pin="VIB" pad="3"/>+ <connect gate="G$1" pin="VIC" pad="4"/>+ <connect gate="G$1" pin="VOD" pad="5"/>+ <connect gate="G$1" pin="VOE" pad="6"/>+ <connect gate="G$1" pin="VOF" pad="7"/>+ <connect gate="G$1" pin="GND1" pad="8"/>+ <connect gate="G$1" pin="VDD2" pad="16"/>+ <connect gate="G$1" pin="VOA" pad="15"/>+ <connect gate="G$1" pin="VOB" pad="14"/>+ <connect gate="G$1" pin="VOC" pad="13"/>+ <connect gate="G$1" pin="VID" pad="12"/>+ <connect gate="G$1" pin="VIE" pad="11"/>+ <connect gate="G$1" pin="VIF" pad="10"/>+ <connect gate="G$1" pin="GND2" pad="9"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
adum163n1brz-rl7.stepadded+10625@@ -0,0 +1,10625 @@+ISO-10303-21;+HEADER;+/* SOIC-16_3.9x9.9mm_P1.27mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2017, kicad StepUp+ * + * This work is licensed under the [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode), + * with the following exception:+ * To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', + * then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided + * as part of the 'Licensed Material'.+ * You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement.+ * However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. + * Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception.+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * *USE 3D CAD DATA AT YOUR OWN RISK*+ * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.*+ * + */++FILE_DESCRIPTION(+/* description */ ('model of SOIC-16_3.9x9.9mm_P1.27mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'SOIC-16_3.9x9.9mm_P1.27mm.step',+/* time_stamp */ '2017-12-18T00:39:18',+/* author */ ('kicad StepUp','ksu'),+/* organization */ ('FreeCAD'),+/* preprocessor_version */ 'OCC',+/* originating_system */ 'kicad StepUp',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1 = APPLICATION_PROTOCOL_DEFINITION('international standard',+'automotive_design',2000,#2);+#2 = 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docs/adum163n1brz-rl7-datasheet.pdfadded⋯ 1 unchanged line ⋯
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Pin 1-3 rows are on page 18 and pins 4-16 continue on page 19; source_page reflects that split.; The datasheet gives only the 1.7 V to 5.5 V supply range as a pin-level limit. Output and input desc"+ ],+ "pages_sent": 17,+ "cost_usd": 0.0769,+ "at": "2026-10-31T03:53:49"+ },+ "datasheet": {+ "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM160N-161N-162N-163N.pdf",+ "pages": 25,+ "sha256": "716242daccaa34f4",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adum163n1brz-rl7.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "367909b9fba0fc6e5f8ddfd494d69d39e1abbd361f14de92a0594a200138f1fc",+ "checked": "2026-10-31",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adum163n1brz-rl7-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3733d17d43eebddea11082e831c15a8aca88426340e8732d69102f755aee7e2e",+ "checked": "2026-10-31",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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