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ADS8568SPMR
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Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+101@@ -0,0 +1,101 @@+# ADS8568SPMR++**Texas Instruments** · Analog To Digital Converters (ADC) · LQFP-64(10x10)++ADS8568SPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | HVSS | power_in | Negative supply voltage for the analog inputs; decouple according to Power Supply Recommendations section. |+| 2 | CH_D1 | input | Analog input of channel D1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode; can be powered down using CONFIG bit C18 (PD_D). |+| 3 | REFDN | input | Decoupling capacitor input for reference of channel pair D; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 4 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 5 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 6 | REFDP | input | Decoupling capacitor input for channel pair D reference; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 7 | CH_D0 | input | Analog input of channel D0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode; can be powered down using CONFIG bit C18 (PD_D). |+| 8 | PAR/SER | input | Interface mode selection input; when low, parallel interface is selected; when high, serial interface is enabled. |+| 9 | STBY | input | Standby mode input; in hardware mode (HW/SW = 0), when low, entire device is powered down; when high, device operates in normal mode; in software mode, connect to DGND or DVDD. |+| 10 | RESET | input | Reset input, active high; aborts any ongoing conversions and resets internal CONFIG register to 000003FFh; valid reset pulse must be at least 50 ns long. |+| 11 | REFEN/WR | input | Internal reference enable/write input; in hardware mode, when high, internal reference is enabled; when low, internal reference is disabled; in software mode, write input or connect to DGND/DVDD. |+| 12 | RD | input | Read data input; in parallel mode, when low, parallel data output is enabled (if CS = 0); when high, data output is disabled; in serial mode, must be connected to DGND. |+| 13 | CS/FS | input | Chip-select input (parallel mode); when low, parallel interface is enabled; when high, interface is disabled; in serial mode, frame synchronization input where FS falling edge controls frame transfer. |+| 14 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 15 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 16 | DB15/SDO_D | bidirectional | Data bit 15 (MSB) input/output in parallel mode; data output for channel pair D in serial mode (when SEL_CD = 1); when SEL_CD = 0, tie this pin to DGND. |+| 17 | DB14/SDO_C | bidirectional | Data bit 14 input/output in parallel mode; data output for channel pair C in serial mode (when SEL_CD = 1); when SEL_CD = 0, tie this pin to DGND. |+| 18 | DB13/SDO_B | bidirectional | Data bit 13 input/output in parallel mode; data output for channel pair B in serial mode (when SEL_B = 1); when SEL_B = 0, tie this pin to DGND. |+| 19 | DB12/SDO_A | bidirectional | Data bit 12 input/output in parallel mode; data output for channel pair A in serial mode where SDO_A is always active; single data output for all eight channels when SEL_CD = 0 and SEL_B = 0. |+| 20 | DB11/REFBUFEN | bidirectional | Data bit 11 input/output in parallel mode; in hardware mode (HW/SW = 0), reference buffer enable input, when low all internal reference buffers are enabled; in software mode, connect to DGND or DVDD. |+| 21 | DB10/SCLK | bidirectional | Data bit 10 input/output in parallel mode; serial interface clock input in serial mode with serial clock frequency of 0.1 to 45 MHz and duty cycle of 40% to 60%. |+| 22 | DB9/SDI | bidirectional | Data bit 9 input/output in parallel mode; in hardware mode (HW/SW = 0), connect to DGND; in software mode (HW/SW = 1), serial data input latched with SCLK falling edge. |+| 23 | DB8/DCEN | bidirectional | Data bit 8 input/output in parallel mode; daisy-chain enable input in serial mode; when high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D]; if daisy-chain mode not used, connect to DGND. |+| 24 | DGND | power_in | Buffer I/O ground; connect to digital ground plane. |+| 25 | DVDD | power_in | Buffer I/O supply voltage; connect to digital supply; decouple according to Power Supply Recommendations section. |+| 26 | DB7 | bidirectional | Data bit 7 input/output in parallel mode; must be connected to DGND in serial mode. |+| 27 | DB6/SEL_B | bidirectional | Data bit 6 input/output in parallel mode; in serial mode, select SDO_B input where when low, SDO_B is disabled and data from all eight channels available on SDO_A; when high and SEL_CD = 0, data from channel pairs B and D available on SDO_B. |+| 28 | DB5/SEL_CD | bidirectional | Data bit 5 input/output in parallel mode; in serial mode, select SDO_C and SDO_D input where when high, data from channel pair C available on SDO_C and channel pair D available on SDO_D. |+| 29 | DB4 | bidirectional | Data bit 4 input/output in parallel mode; must be connected to DGND in serial mode. |+| 30 | DB3/DCIN_A | bidirectional | Data bit 3 input/output in parallel mode; in serial mode, daisy-chain data input for SDO_A of the previous device in chain (when DCEN = 1); when DCEN = 0, connect to DGND. |+| 31 | DB2/DCIN_B | bidirectional | Data bit 2 input/output in parallel mode; in serial mode, daisy-chain data input for SDO_B of the previous device in chain (when DCEN = 1 and SEL_B = 1); when DCEN = 0, connect to DGND. |+| 32 | DB1/DCIN_C | bidirectional | Data bit 1 input/output in parallel mode; in serial mode, daisy-chain data input for SDO_C of the previous device in chain (when DCEN = 1 and SEL_CD = 1); when DCEN = 0, connect to DGND. |+| 33 | DB0/DCIN_D | bidirectional | Data bit 0 (LSB) input/output in parallel mode; in serial mode, daisy-chain data input for SDO_D of the previous device in chain (when DCEN = 1 and SEL_CD = 1); when DCEN = 0, connect to DGND. |+| 34 | RANGE/XCLK | input | In hardware mode, analog input voltage range select input; when low, input voltage range is ±4 VREF; when high, input voltage range is ±2 VREF; in software mode, external conversion clock input (if CONFIG bit C29 = 1) or internal conversion clock output (if CONFIG bit C28 = 1); if not used, connect to DGND. |+| 35 | BUSY/INT | output | When CONFIG bit C27 = 0, converter busy status output transitioning high at conversion start and low when channel pair conversion completes; when CONFIG bit C27 = 1, interrupt output transitioning high after conversion completes; polarity controlled by CONFIG bit C26 (BUSY_L/H). |+| 36 | ASLEEP | input | Auto-sleep enable input; when low, device operates in normal mode; when high, device functions in auto-sleep mode where hold mode and actual conversion activated six conversion clock cycles after issuing CONVST_x for power saving at lower data rates. |+| 37 | CONVST_A | input | Conversion start of channel pair A (master channel pair, always active); rising edge initiates simultaneous conversion of analog signals at inputs CH_A[1:0]; resets internal channel state machine causing data output to start with conversion results of channel A0 with next read access. |+| 38 | CONVST_B | input | Conversion start of channel pair B; rising edge initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. |+| 39 | CONVST_C | input | Conversion start of channel pair C; rising edge initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. |+| 40 | CONVST_D | input | Conversion start of channel pair D; rising edge initiates simultaneous conversion of analog signals at inputs CH_D[1:0]. |+| 41 | HW/SW | input | Mode selection input; when low, hardware mode is selected and device functions according to settings of external pins; when high, software mode is selected and device configured by writing to CONFIG register. |+| 42 | CH_A0 | input | Analog input of channel A0 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode; must run at highest data rate when channel pairs used at different data rates. |+| 43 | REFAP | input | Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 44 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 45 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 46 | REFAN | input | Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 47 | CH_A1 | input | Analog input of channel A1 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode; must run at highest data rate when channel pairs used at different data rates. |+| 48 | HVDD | power_in | Positive supply voltage for the analog inputs; decouple according to Power Supply Recommendations section. |+| 49 | CH_B0 | input | Analog input of channel B0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode. |+| 50 | REFBP | input | Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 51 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 52 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 53 | REFBN | input | Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 54 | CH_B1 | input | Analog input of channel B1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode. |+| 55 | REFN | input | Negative reference input/output pin; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 56 | REFIO | bidirectional | Reference voltage input/output; internal reference enabled by REFEN/WR pin in hardware mode or CONFIG bit C15 (REFEN) in software mode; output value controlled by internal DAC and CONFIG bits C[9:0]; connect to decoupling capacitor (100 nF minimum, 470 nF recommended). |+| 57 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 58 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 59 | CH_C1 | input | Analog input of channel C1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode. |+| 60 | REFCN | input | Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor and AGND according to Power Supply Recommendations section. |+| 61 | AVDD | power_in | Analog power supply; decouple according to Power Supply Recommendations section. |+| 62 | AGND | power_in | Analog ground; connect to the analog ground plane. |+| 63 | REFCP | input | Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor according to Power Supply Recommendations section. |+| 64 | CH_C0 | input | Analog input of channel C0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-64(10x10) |+| Category | Data Acquisition |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `ADS8568SPMR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `ads8568spmr-etched.step` / `ads8568spmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads8568spmr.step` / `ads8568spmr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads8548) (62 pp, sha256 `c3931541d3d34e55`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads8568spmr-datasheet.pdf)
page.jsonadded+479@@ -0,0 +1,479 @@+{+ "slug": "ads8568spmr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADC), LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "ads8568spmr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ads8568spmr.kicad_sym",+ "ads8568spmr.kicad_mod",+ "ads8568spmr.glb",+ "ads8568spmr.step",+ "ads8568spmr.lbr",+ "docs/hero.png",+ "docs/ads8568spmr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADS8568SPMR",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ads8548",+ "parts": {+ "symbol": "ads8568spmr.kicad_sym",+ "footprint": "ads8568spmr.kicad_mod",+ "model_3d": "ads8568spmr-etched.glb",+ "model_3d_plain": "ads8568spmr.glb",+ "model_3d_step": "ads8568spmr-etched.step",+ "model_3d_step_plain": "ads8568spmr.step",+ "lbr": "ads8568spmr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2670843"+ },+ "pins": [+ {+ "number": "1",+ "name": "HVSS",+ "type": "power_in",+ "description": "Negative supply voltage for the analog inputs; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "2",+ "name": "CH_D1",+ "type": "input",+ "description": "Analog input of channel D1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode; can be powered down using CONFIG bit C18 (PD_D)."+ },+ {+ "number": "3",+ "name": "REFDN",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair D; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "4",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "5",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "6",+ "name": "REFDP",+ "type": "input",+ "description": "Decoupling capacitor input for channel pair D reference; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "7",+ "name": "CH_D0",+ "type": "input",+ "description": "Analog input of channel D0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C19 (RANGE_D) in software mode; can be powered down using CONFIG bit C18 (PD_D)."+ },+ {+ "number": "8",+ "name": "PAR/SER",+ "type": "input",+ "description": "Interface mode selection input; when low, parallel interface is selected; when high, serial interface is enabled."+ },+ {+ "number": "9",+ "name": "STBY",+ "type": "input",+ "description": "Standby mode input; in hardware mode (HW/SW = 0), when low, entire device is powered down; when high, device operates in normal mode; in software mode, connect to DGND or DVDD."+ },+ {+ "number": "10",+ "name": "RESET",+ "type": "input",+ "description": "Reset input, active high; aborts any ongoing conversions and resets internal CONFIG register to 000003FFh; valid reset pulse must be at least 50 ns long."+ },+ {+ "number": "11",+ "name": "REFEN/WR",+ "type": "input",+ "description": "Internal reference enable/write input; in hardware mode, when high, internal reference is enabled; when low, internal reference is disabled; in software mode, write input or connect to DGND/DVDD."+ },+ {+ "number": "12",+ "name": "RD",+ "type": "input",+ "description": "Read data input; in parallel mode, when low, parallel data output is enabled (if CS = 0); when high, data output is disabled; in serial mode, must be connected to DGND."+ },+ {+ "number": "13",+ "name": "CS/FS",+ "type": "input",+ "description": "Chip-select input (parallel mode); when low, parallel interface is enabled; when high, interface is disabled; in serial mode, frame synchronization input where FS falling edge controls frame transfer."+ },+ {+ "number": "14",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "15",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "16",+ "name": "DB15/SDO_D",+ "type": "bidirectional",+ "description": "Data bit 15 (MSB) input/output in parallel mode; data output for channel pair D in serial mode (when SEL_CD = 1); when SEL_CD = 0, tie this pin to DGND."+ },+ {+ "number": "17",+ "name": "DB14/SDO_C",+ "type": "bidirectional",+ "description": "Data bit 14 input/output in parallel mode; data output for channel pair C in serial mode (when SEL_CD = 1); when SEL_CD = 0, tie this pin to DGND."+ },+ {+ "number": "18",+ "name": "DB13/SDO_B",+ "type": "bidirectional",+ "description": "Data bit 13 input/output in parallel mode; data output for channel pair B in serial mode (when SEL_B = 1); when SEL_B = 0, tie this pin to DGND."+ },+ {+ "number": "19",+ "name": "DB12/SDO_A",+ "type": "bidirectional",+ "description": "Data bit 12 input/output in parallel mode; data output for channel pair A in serial mode where SDO_A is always active; single data output for all eight channels when SEL_CD = 0 and SEL_B = 0."+ },+ {+ "number": "20",+ "name": "DB11/REFBUFEN",+ "type": "bidirectional",+ "description": "Data bit 11 input/output in parallel mode; in hardware mode (HW/SW = 0), reference buffer enable input, when low all internal reference buffers are enabled; in software mode, connect to DGND or DVDD."+ },+ {+ "number": "21",+ "name": "DB10/SCLK",+ "type": "bidirectional",+ "description": "Data bit 10 input/output in parallel mode; serial interface clock input in serial mode with serial clock frequency of 0.1 to 45 MHz and duty cycle of 40% to 60%."+ },+ {+ "number": "22",+ "name": "DB9/SDI",+ "type": "bidirectional",+ "description": "Data bit 9 input/output in parallel mode; in hardware mode (HW/SW = 0), connect to DGND; in software mode (HW/SW = 1), serial data input latched with SCLK falling edge."+ },+ {+ "number": "23",+ "name": "DB8/DCEN",+ "type": "bidirectional",+ "description": "Data bit 8 input/output in parallel mode; daisy-chain enable input in serial mode; when high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D]; if daisy-chain mode not used, connect to DGND."+ },+ {+ "number": "24",+ "name": "DGND",+ "type": "power_in",+ "description": "Buffer I/O ground; connect to digital ground plane."+ },+ {+ "number": "25",+ "name": "DVDD",+ "type": "power_in",+ "description": "Buffer I/O supply voltage; connect to digital supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "26",+ "name": "DB7",+ "type": "bidirectional",+ "description": "Data bit 7 input/output in parallel mode; must be connected to DGND in serial mode."+ },+ {+ "number": "27",+ "name": "DB6/SEL_B",+ "type": "bidirectional",+ "description": "Data bit 6 input/output in parallel mode; in serial mode, select SDO_B input where when low, SDO_B is disabled and data from all eight channels available on SDO_A; when high and SEL_CD = 0, data from channel pairs B and D available on SDO_B."+ },+ {+ "number": "28",+ "name": "DB5/SEL_CD",+ "type": "bidirectional",+ "description": "Data bit 5 input/output in parallel mode; in serial mode, select SDO_C and SDO_D input where when high, data from channel pair C available on SDO_C and channel pair D available on SDO_D."+ },+ {+ "number": "29",+ "name": "DB4",+ "type": "bidirectional",+ "description": "Data bit 4 input/output in parallel mode; must be connected to DGND in serial mode."+ },+ {+ "number": "30",+ "name": "DB3/DCIN_A",+ "type": "bidirectional",+ "description": "Data bit 3 input/output in parallel mode; in serial mode, daisy-chain data input for SDO_A of the previous device in chain (when DCEN = 1); when DCEN = 0, connect to DGND."+ },+ {+ "number": "31",+ "name": "DB2/DCIN_B",+ "type": "bidirectional",+ "description": "Data bit 2 input/output in parallel mode; in serial mode, daisy-chain data input for SDO_B of the previous device in chain (when DCEN = 1 and SEL_B = 1); when DCEN = 0, connect to DGND."+ },+ {+ "number": "32",+ "name": "DB1/DCIN_C",+ "type": "bidirectional",+ "description": "Data bit 1 input/output in parallel mode; in serial mode, daisy-chain data input for SDO_C of the previous device in chain (when DCEN = 1 and SEL_CD = 1); when DCEN = 0, connect to DGND."+ },+ {+ "number": "33",+ "name": "DB0/DCIN_D",+ "type": "bidirectional",+ "description": "Data bit 0 (LSB) input/output in parallel mode; in serial mode, daisy-chain data input for SDO_D of the previous device in chain (when DCEN = 1 and SEL_CD = 1); when DCEN = 0, connect to DGND."+ },+ {+ "number": "34",+ "name": "RANGE/XCLK",+ "type": "input",+ "description": "In hardware mode, analog input voltage range select input; when low, input voltage range is ±4 VREF; when high, input voltage range is ±2 VREF; in software mode, external conversion clock input (if CONFIG bit C29 = 1) or internal conversion clock output (if CONFIG bit C28 = 1); if not used, connect to DGND."+ },+ {+ "number": "35",+ "name": "BUSY/INT",+ "type": "output",+ "description": "When CONFIG bit C27 = 0, converter busy status output transitioning high at conversion start and low when channel pair conversion completes; when CONFIG bit C27 = 1, interrupt output transitioning high after conversion completes; polarity controlled by CONFIG bit C26 (BUSY_L/H)."+ },+ {+ "number": "36",+ "name": "ASLEEP",+ "type": "input",+ "description": "Auto-sleep enable input; when low, device operates in normal mode; when high, device functions in auto-sleep mode where hold mode and actual conversion activated six conversion clock cycles after issuing CONVST_x for power saving at lower data rates."+ },+ {+ "number": "37",+ "name": "CONVST_A",+ "type": "input",+ "description": "Conversion start of channel pair A (master channel pair, always active); rising edge initiates simultaneous conversion of analog signals at inputs CH_A[1:0]; resets internal channel state machine causing data output to start with conversion results of channel A0 with next read access."+ },+ {+ "number": "38",+ "name": "CONVST_B",+ "type": "input",+ "description": "Conversion start of channel pair B; rising edge initiates simultaneous conversion of analog signals at inputs CH_B[1:0]."+ },+ {+ "number": "39",+ "name": "CONVST_C",+ "type": "input",+ "description": "Conversion start of channel pair C; rising edge initiates simultaneous conversion of analog signals at inputs CH_C[1:0]."+ },+ {+ "number": "40",+ "name": "CONVST_D",+ "type": "input",+ "description": "Conversion start of channel pair D; rising edge initiates simultaneous conversion of analog signals at inputs CH_D[1:0]."+ },+ {+ "number": "41",+ "name": "HW/SW",+ "type": "input",+ "description": "Mode selection input; when low, hardware mode is selected and device functions according to settings of external pins; when high, software mode is selected and device configured by writing to CONFIG register."+ },+ {+ "number": "42",+ "name": "CH_A0",+ "type": "input",+ "description": "Analog input of channel A0 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode; must run at highest data rate when channel pairs used at different data rates."+ },+ {+ "number": "43",+ "name": "REFAP",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "44",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "45",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "46",+ "name": "REFAN",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair A; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "47",+ "name": "CH_A1",+ "type": "input",+ "description": "Analog input of channel A1 (master channel pair, always active); input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C24 (RANGE_A) in software mode; must run at highest data rate when channel pairs used at different data rates."+ },+ {+ "number": "48",+ "name": "HVDD",+ "type": "power_in",+ "description": "Positive supply voltage for the analog inputs; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "49",+ "name": "CH_B0",+ "type": "input",+ "description": "Analog input of channel B0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode."+ },+ {+ "number": "50",+ "name": "REFBP",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "51",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "52",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "53",+ "name": "REFBN",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair B; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "54",+ "name": "CH_B1",+ "type": "input",+ "description": "Analog input of channel B1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C23 (RANGE_B) in software mode."+ },+ {+ "number": "55",+ "name": "REFN",+ "type": "input",+ "description": "Negative reference input/output pin; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "56",+ "name": "REFIO",+ "type": "bidirectional",+ "description": "Reference voltage input/output; internal reference enabled by REFEN/WR pin in hardware mode or CONFIG bit C15 (REFEN) in software mode; output value controlled by internal DAC and CONFIG bits C[9:0]; connect to decoupling capacitor (100 nF minimum, 470 nF recommended)."+ },+ {+ "number": "57",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "58",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "59",+ "name": "CH_C1",+ "type": "input",+ "description": "Analog input of channel C1; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode."+ },+ {+ "number": "60",+ "name": "REFCN",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor and AGND according to Power Supply Recommendations section."+ },+ {+ "number": "61",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; decouple according to Power Supply Recommendations section."+ },+ {+ "number": "62",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to the analog ground plane."+ },+ {+ "number": "63",+ "name": "REFCP",+ "type": "input",+ "description": "Decoupling capacitor input for reference of channel pair C; connect to decoupling capacitor according to Power Supply Recommendations section."+ },+ {+ "number": "64",+ "name": "CH_C0",+ "type": "input",+ "description": "Analog input of channel C0; input voltage range controlled by RANGE pin in hardware mode or CONFIG bit C21 (RANGE_C) in software mode."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: All pin information extracted from Pin Configuration and Functions (pages 4-8), Pin Functions table "+ ],+ "pages_sent": 62,+ "cost_usd": 0.8498,+ "at": "2026-09-23T18:08:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads8548",+ "pages": 62,+ "sha256": "c3931541d3d34e55",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}