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ADS1294IPAG
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Texas Instruments Analog Front End (AFE), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+101@@ -0,0 +1,101 @@+# ADS1294IPAG++**Texas Instruments** · Analog Front End (AFE) · TQFP-64(10x10)++ADS1294IPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN8N | input | Differential analog negative input 8, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 2 | IN8P | input | Differential analog positive input 8, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 3 | IN7N | input | Differential analog negative input 7, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 4 | IN7P | input | Differential analog positive input 7, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 5 | IN6N | input | Differential analog negative input 6, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 6 | IN6P | input | Differential analog positive input 6, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 7 | IN5N | input | Differential analog negative input 5, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 8 | IN5P | input | Differential analog positive input 5, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 9 | IN4N | input | Differential analog negative input 4; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 10 | IN4P | input | Differential analog positive input 4; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 11 | IN3N | input | Differential analog negative input 3; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 12 | IN3P | input | Differential analog positive input 3; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 13 | IN2N | input | Differential analog negative input 2; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 14 | IN2P | input | Differential analog positive input 2; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 15 | IN1N | input | Differential analog negative input 1; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 16 | IN1P | input | Differential analog positive input 1; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V. |+| 17 | TESTP_PACE_OUT1 | bidirectional | Internal test signal or single-ended buffered output for pace detection, selected by register settings; can also serve as an auxiliary differential input when hardware pace detection is not used. |+| 18 | TESTN_PACE_OUT2 | bidirectional | Internal test signal or single-ended buffered output for pace detection, selected by register settings; can also serve as an auxiliary differential input when hardware pace detection is not used. |+| 19 | AVDD | power_in | Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors. |+| 20 | AVSS | power_in | Analog ground, the reference for AVDD and the internal reference generation. |+| 21 | AVDD | power_in | Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors. |+| 22 | AVDD | power_in | Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors. |+| 23 | AVSS | power_in | Analog ground, the reference for AVDD and the internal reference generation. |+| 24 | VREFP | bidirectional | Positive reference input/output; the reference is VREFP - VREFN, which is 2.5 V on a 3 V supply or 4 V on a 5 V supply, and VREFP must be between AVSS and AVSS + 2.5 V. |+| 25 | VREFN | input | Negative reference input; it must be connected to AVSS when the internal reference is used. |+| 26 | VCAP4 | passive | Analog bypass capacitor node; connect a 1 µF capacitor to AVSS. |+| 27 | NC | unconnected | No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor. |+| 28 | VCAP1 | passive | Analog bypass capacitor node; connect a 22 µF capacitor to AVSS. |+| 29 | NC | unconnected | No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor. |+| 30 | VCAP2 | passive | Analog bypass capacitor node; connect a 1 µF capacitor to AVSS. |+| 31 | RESV1 | input | Reserved for future use; must be connected to logic low (DGND). |+| 32 | AVSS | power_in | Analog ground, the reference for AVDD and the internal reference generation. |+| 33 | DGND | power_in | Digital ground. |+| 34 | DIN | input | SPI data input; it is latched on the falling edge of SCLK. |+| 35 | PWDN | input | Power-down input, active low; pulling it low powers down all on-chip circuits. |+| 36 | RESET | input | System reset input, active low; hold low for the minimum pulse width before releasing it. |+| 37 | CLK | bidirectional | External master clock input or internal oscillator clock output; the external clock is 2.048 MHz nominal (1.94 MHz to 2.25 MHz) when CLKSEL = 0. |+| 38 | START | input | Start conversion input; the digital input must stay within DGND to DVDD. |+| 39 | CS | input | SPI chip select, active low; it must stay low for the full serial transaction. |+| 40 | SCLK | input | SPI serial clock input, with Schmitt-trigger input; it should be kept free of noise. |+| 41 | DAISY_IN | input | Daisy-chain input; tie to DGND when not used. |+| 42 | GPIO1 | bidirectional | General-purpose digital I/O pin 1; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused). |+| 43 | DOUT | output | SPI data output; data is shifted out on the rising edge of SCLK, and the pin goes high impedance when CS is high. |+| 44 | GPIO2 | bidirectional | General-purpose digital I/O pin 2; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused). |+| 45 | GPIO3 | bidirectional | General-purpose digital I/O pin 3; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused). |+| 46 | GPIO4 | bidirectional | General-purpose digital I/O pin 4; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused). |+| 47 | DRDY | output | Data ready output, active low; it goes low when new conversion data is available. |+| 48 | DVDD | power_in | Digital supply; DVDD must be 1.65 V to 3.6 V and it should be decoupled with 1 µF and 0.1 µF capacitors. |+| 49 | DGND | power_in | Digital ground. |+| 50 | DVDD | power_in | Digital supply; DVDD must be 1.65 V to 3.6 V and it should be decoupled with 1 µF and 0.1 µF capacitors. |+| 51 | DGND | power_in | Digital ground. |+| 52 | CLKSEL | input | Master clock select; low selects the external clock on CLK, high selects the internal oscillator. |+| 53 | AVSS1 | power_in | Analog ground for the charge pump; connect it in a star configuration to AVSS. |+| 54 | AVDD1 | power_in | Analog supply for the charge pump, which has transients at fCLK; connect it in a star configuration to AVDD. |+| 55 | VCAP3 | passive | Internally generated AVDD + 1.9 V node; connect a 1 µF capacitor to AVSS. |+| 56 | AVDD | power_in | Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors. |+| 57 | AVSS | power_in | Analog ground, the reference for AVDD and the internal reference generation. |+| 58 | AVSS | power_in | Analog ground, the reference for AVDD and the internal reference generation. |+| 59 | AVDD | power_in | Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors. |+| 60 | RLDREF | input | Right-leg drive non-inverting input, used as the RLD reference voltage. |+| 61 | RLDINV | bidirectional | Right-leg drive inverting input; it connects to the RLD amplifier feedback network. |+| 62 | RLDIN | input | Multiplexer input for the right-leg drive signal; tie it to the channel mux per the datasheet configuration (tie to AVDD if unused). |+| 63 | RLDOUT | output | Right-leg drive amplifier output, which drives the patient through the external feedback network. |+| 64 | WCT | output | Wilson central terminal output; its drive is limited, so it must be buffered before driving low-impedance loads and it is intended for very high input impedance (typically above 500 MΩ). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-64(10x10) |+| Category | Data Acquisition |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `ADS1294IPAG`+- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`+- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `ads1294ipag-etched.step` / `ads1294ipag-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1294ipag.step` / `ads1294ipag.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1294) (113 pp, sha256 `a8830f56bfd11d1b`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads1294ipag-datasheet.pdf)
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tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "2",+ "name": "IN8P",+ "type": "input",+ "description": "Differential analog positive input 8, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "3",+ "name": "IN7N",+ "type": "input",+ "description": "Differential analog negative input 7, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "4",+ "name": "IN7P",+ "type": "input",+ "description": "Differential analog positive input 7, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "5",+ "name": "IN6N",+ "type": "input",+ "description": "Differential analog negative input 6, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "6",+ "name": "IN6P",+ "type": "input",+ "description": "Differential analog positive input 6, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "7",+ "name": "IN5N",+ "type": "input",+ "description": "Differential analog negative input 5, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "8",+ "name": "IN5P",+ "type": "input",+ "description": "Differential analog positive input 5, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "9",+ "name": "IN4N",+ "type": "input",+ "description": "Differential analog negative input 4; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "10",+ "name": "IN4P",+ "type": "input",+ "description": "Differential analog positive input 4; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "11",+ "name": "IN3N",+ "type": "input",+ "description": "Differential analog negative input 3; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "12",+ "name": "IN3P",+ "type": "input",+ "description": "Differential analog positive input 3; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "13",+ "name": "IN2N",+ "type": "input",+ "description": "Differential analog negative input 2; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "14",+ "name": "IN2P",+ "type": "input",+ "description": "Differential analog positive input 2; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "15",+ "name": "IN1N",+ "type": "input",+ "description": "Differential analog negative input 1; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "16",+ "name": "IN1P",+ "type": "input",+ "description": "Differential analog positive input 1; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V."+ },+ {+ "number": "17",+ "name": "TESTP_PACE_OUT1",+ "type": "bidirectional",+ "description": "Internal test signal or single-ended buffered output for pace detection, selected by register settings; can also serve as an auxiliary differential input when hardware pace detection is not used."+ },+ {+ "number": "18",+ "name": "TESTN_PACE_OUT2",+ "type": "bidirectional",+ "description": "Internal test signal or single-ended buffered output for pace detection, selected by register settings; can also serve as an auxiliary differential input when hardware pace detection is not used."+ },+ {+ "number": "19",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "20",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, the reference for AVDD and the internal reference generation."+ },+ {+ "number": "21",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "22",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "23",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, the reference for AVDD and the internal reference generation."+ },+ {+ "number": "24",+ "name": "VREFP",+ "type": "bidirectional",+ "description": "Positive reference input/output; the reference is VREFP - VREFN, which is 2.5 V on a 3 V supply or 4 V on a 5 V supply, and VREFP must be between AVSS and AVSS + 2.5 V."+ },+ {+ "number": "25",+ "name": "VREFN",+ "type": "input",+ "description": "Negative reference input; it must be connected to AVSS when the internal reference is used."+ },+ {+ "number": "26",+ "name": "VCAP4",+ "type": "passive",+ "description": "Analog bypass capacitor node; connect a 1 µF capacitor to AVSS."+ },+ {+ "number": "27",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor."+ },+ {+ "number": "28",+ "name": "VCAP1",+ "type": "passive",+ "description": "Analog bypass capacitor node; connect a 22 µF capacitor to AVSS."+ },+ {+ "number": "29",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor."+ },+ {+ "number": "30",+ "name": "VCAP2",+ "type": "passive",+ "description": "Analog bypass capacitor node; connect a 1 µF capacitor to AVSS."+ },+ {+ "number": "31",+ "name": "RESV1",+ "type": "input",+ "description": "Reserved for future use; must be connected to logic low (DGND)."+ },+ {+ "number": "32",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, the reference for AVDD and the internal reference generation."+ },+ {+ "number": "33",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "34",+ "name": "DIN",+ "type": "input",+ "description": "SPI data input; it is latched on the falling edge of SCLK."+ },+ {+ "number": "35",+ "name": "PWDN",+ "type": "input",+ "description": "Power-down input, active low; pulling it low powers down all on-chip circuits."+ },+ {+ "number": "36",+ "name": "RESET",+ "type": "input",+ "description": "System reset input, active low; hold low for the minimum pulse width before releasing it."+ },+ {+ "number": "37",+ "name": "CLK",+ "type": "bidirectional",+ "description": "External master clock input or internal oscillator clock output; the external clock is 2.048 MHz nominal (1.94 MHz to 2.25 MHz) when CLKSEL = 0."+ },+ {+ "number": "38",+ "name": "START",+ "type": "input",+ "description": "Start conversion input; the digital input must stay within DGND to DVDD."+ },+ {+ "number": "39",+ "name": "CS",+ "type": "input",+ "description": "SPI chip select, active low; it must stay low for the full serial transaction."+ },+ {+ "number": "40",+ "name": "SCLK",+ "type": "input",+ "description": "SPI serial clock input, with Schmitt-trigger input; it should be kept free of noise."+ },+ {+ "number": "41",+ "name": "DAISY_IN",+ "type": "input",+ "description": "Daisy-chain input; tie to DGND when not used."+ },+ {+ "number": "42",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O pin 1; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused)."+ },+ {+ "number": "43",+ "name": "DOUT",+ "type": "output",+ "description": "SPI data output; data is shifted out on the rising edge of SCLK, and the pin goes high impedance when CS is high."+ },+ {+ "number": "44",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O pin 2; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused)."+ },+ {+ "number": "45",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O pin 3; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused)."+ },+ {+ "number": "46",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O pin 4; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused)."+ },+ {+ "number": "47",+ "name": "DRDY",+ "type": "output",+ "description": "Data ready output, active low; it goes low when new conversion data is available."+ },+ {+ "number": "48",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply; DVDD must be 1.65 V to 3.6 V and it should be decoupled with 1 µF and 0.1 µF capacitors."+ },+ {+ "number": "49",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "50",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply; DVDD must be 1.65 V to 3.6 V and it should be decoupled with 1 µF and 0.1 µF capacitors."+ },+ {+ "number": "51",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "52",+ "name": "CLKSEL",+ "type": "input",+ "description": "Master clock select; low selects the external clock on CLK, high selects the internal oscillator."+ },+ {+ "number": "53",+ "name": "AVSS1",+ "type": "power_in",+ "description": "Analog ground for the charge pump; connect it in a star configuration to AVSS."+ },+ {+ "number": "54",+ "name": "AVDD1",+ "type": "power_in",+ "description": "Analog supply for the charge pump, which has transients at fCLK; connect it in a star configuration to AVDD."+ },+ {+ "number": "55",+ "name": "VCAP3",+ "type": "passive",+ "description": "Internally generated AVDD + 1.9 V node; connect a 1 µF capacitor to AVSS."+ },+ {+ "number": "56",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "57",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, the reference for AVDD and the internal reference generation."+ },+ {+ "number": "58",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground, the reference for AVDD and the internal reference generation."+ },+ {+ "number": "59",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "60",+ "name": "RLDREF",+ "type": "input",+ "description": "Right-leg drive non-inverting input, used as the RLD reference voltage."+ },+ {+ "number": "61",+ "name": "RLDINV",+ "type": "bidirectional",+ "description": "Right-leg drive inverting input; it connects to the RLD amplifier feedback network."+ },+ {+ "number": "62",+ "name": "RLDIN",+ "type": "input",+ "description": "Multiplexer input for the right-leg drive signal; tie it to the channel mux per the datasheet configuration (tie to AVDD if unused)."+ },+ {+ "number": "63",+ "name": "RLDOUT",+ "type": "output",+ "description": "Right-leg drive amplifier output, which drives the patient through the external feedback network."+ },+ {+ "number": "64",+ "name": "WCT",+ "type": "output",+ "description": "Wilson central terminal output; its drive is limited, so it must be buffered before driving low-impedance loads and it is intended for very high input impedance (typically above 500 MΩ)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Source is a Chinese-translated TI datasheet (SBAS459 / ZHCS313K). Pin numbers and names were taken f; Pin types are KiCad-class mappings of the datasheet's labels: analog inputs mapped to input, analog ; Pins 1-8 (IN5-IN8) are labeled as used only on ADS1296/ADS1298 in the datasheet. For the 4-channel A"+ ],+ "pages_sent": 80,+ "cost_usd": 0.4092,+ "at": "2026-10-08T20:43:19"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads1294",+ "pages": 113,+ "sha256": "a8830f56bfd11d1b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads1294ipag.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "60567e81b0770b6c519104183a7a05ba52dddc11146b5fbe21434fbb5801696c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads1294ipag-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7b716f218250704e4acd775a8394a05e0a300a7c20b0f3357b7befd948aa172d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}