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ADS127L01IPBSR
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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+69@@ -0,0 +1,69 @@+# ADS127L01IPBSR++**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-32(5x5)++ADS127L01IPBSR from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LVDD | power_in | Analog supply pin that is an output of the internal analog LDO with a 1-µF capacitor to AGND when INTLDO=0, and an input to be connected to a 1.8-V supply when INTLDO=1. |+| 2 | CAP1 | output | Modulator common-mode voltage node that requires a 1-µF capacitor connected to AGND. |+| 3 | AINN | input | Negative analog input. |+| 4 | AINP | input | Positive analog input. |+| 5 | AGND | power_in | Analog ground. |+| 6 | AVDD | power_in | Analog supply that requires a 1-µF capacitor connected to AGND. |+| 7 | REXT | input | Analog power-scaling bias resistor pin: 60.4 kΩ to AGND for high-resolution (HR) and low-power (LP) modes, or 120 kΩ to AGND for very-low-power (VLP) mode. |+| 8 | INTLDO | input | LVDD voltage-select digital input, pulled high to AVDD (1 = external LVDD supply) or low to AGND through 10 kΩ (0 = internal LDO). |+| 9 | REFP | input | Positive analog reference input that requires a minimum 10-µF capacitor to REFN. |+| 10 | REFN | input | Negative analog reference input. |+| 11 | CAP2 | output | Reference common-mode voltage node that requires a 1-µF capacitor connected to AGND. |+| 12 | FILTER1 | input | Digital filter select pin (MSB, with FILTER0): 00 = Wideband 1, 01 = Wideband 2, 10 = Low-latency, 11 = reserved; hardware pin to be pulled high to DVDD or low to DGND through 100 kΩ. |+| 13 | FILTER0 | input | Digital filter select pin (LSB, with FILTER1) using the same coding as FILTER1; hardware pin to be pulled high to DVDD or low to DGND through 100 kΩ. |+| 14 | FSMODE | input | Frame-sync mode select: 0 = slave mode, 1 = master mode, applicable to frame-sync interface only with no effect in SPI mode. |+| 15 | OSR1 | input | Oversampling-ratio select pin (MSB, with OSR0) for the decimation filters; for wideband filters 00/01/10/11 select OSR 32/64/128/256, and for the low-latency filter they select OSR 32/128/512/2048. |+| 16 | OSR0 | input | Oversampling-ratio select pin (LSB, with OSR1) using the coding described for OSR1 and dependent on the FILTER[1:0] setting. |+| 17 | START | input | Synchronization input used to start or restart a conversion. |+| 18 | DAISYIN | input | Daisy-chain input that must be tied directly to DGND when devices are not daisy-chained. |+| 19 | DRDY/FSYNC | bidirectional | In SPI mode this is the active-low data-ready output; in frame-sync mode it is the frame-sync input signal; leave floating or tie to DVDD through high-impedance resistor when unused in SPI mode. |+| 20 | DOUT | output | Serial data output. |+| 21 | DIN | input | Serial data input that must be tied directly to DGND when using the frame-sync interface. |+| 22 | SCLK | bidirectional | Serial clock pin, specified as a digital input/output, serving as the serial clock input. |+| 23 | CS | input | Chip select that must be tied directly to DGND when using the frame-sync interface. |+| 24 | CLK | input | Master clock input. |+| 25 | CAP3 | output | Internally generated digital operating voltage that requires a 1-µF capacitor connected to DGND. |+| 26 | DGND | power_in | Digital ground. |+| 27 | DVDD | power_in | Digital supply that requires a 1-µF capacitor connected to DGND. |+| 28 | RESET/PWDN | input | Active-low reset or power-down pin; see the Reset and Power-Down Pin section for hardware design details when using power-down mode. |+| 29 | HR | input | ADC operating mode select: 1 = high-resolution (HR), 0 = low-power (LP) or very-low-power (VLP), with LP/VLP selected by the REXT resistor value. |+| 30 | FORMAT | input | Interface select: 0 = SPI interface, 1 = frame-sync interface; hardware pin to be pulled high to DVDD or low to DGND through 100 kΩ. |+| 31 | AGND | power_in | Analog ground. |+| 32 | AVDD | power_in | Analog supply that must be decoupled to AGND with a 1-µF capacitor. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-32(5x5) |+| Category | Data Acquisition |+| Pins | 32 |++## CAD (KiCad official)++- Symbol: `ADS127L01IPBSR`+- Footprint: `Package_QFP:TQFP-32_5x5mm_P0.5mm`+- 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `ads127l01ipbsr-etched.step` / `ads127l01ipbsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads127l01ipbsr.step` / `ads127l01ipbsr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads127l01) (90 pp, sha256 `7af2117fe188e693`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads127l01ipbsr-datasheet.pdf)
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hardware pin to be pulled high to DVDD or low to DGND through 100 kΩ."+ },+ {+ "number": "13",+ "name": "FILTER0",+ "type": "input",+ "description": "Digital filter select pin (LSB, with FILTER1) using the same coding as FILTER1; hardware pin to be pulled high to DVDD or low to DGND through 100 kΩ."+ },+ {+ "number": "14",+ "name": "FSMODE",+ "type": "input",+ "description": "Frame-sync mode select: 0 = slave mode, 1 = master mode, applicable to frame-sync interface only with no effect in SPI mode."+ },+ {+ "number": "15",+ "name": "OSR1",+ "type": "input",+ "description": "Oversampling-ratio select pin (MSB, with OSR0) for the decimation filters; for wideband filters 00/01/10/11 select OSR 32/64/128/256, and for the low-latency filter they select OSR 32/128/512/2048."+ },+ {+ "number": "16",+ "name": "OSR0",+ "type": "input",+ "description": "Oversampling-ratio select pin (LSB, with OSR1) using the coding described for OSR1 and dependent on the FILTER[1:0] setting."+ },+ {+ "number": "17",+ "name": "START",+ "type": "input",+ "description": "Synchronization input used to start or restart a conversion."+ },+ {+ "number": "18",+ "name": "DAISYIN",+ "type": "input",+ "description": "Daisy-chain input that must be tied directly to DGND when devices are not daisy-chained."+ },+ {+ "number": "19",+ "name": "DRDY/FSYNC",+ "type": "bidirectional",+ "description": "In SPI mode this is the active-low data-ready output; in frame-sync mode it is the frame-sync input signal; leave floating or tie to DVDD through high-impedance resistor when unused in SPI mode."+ },+ {+ "number": "20",+ "name": "DOUT",+ "type": "output",+ "description": "Serial data output."+ },+ {+ "number": "21",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input that must be tied directly to DGND when using the frame-sync interface."+ },+ {+ "number": "22",+ "name": "SCLK",+ "type": "bidirectional",+ "description": "Serial clock pin, specified as a digital input/output, serving as the serial clock input."+ },+ {+ "number": "23",+ "name": "CS",+ "type": "input",+ "description": "Chip select that must be tied directly to DGND when using the frame-sync interface."+ },+ {+ "number": "24",+ "name": "CLK",+ "type": "input",+ "description": "Master clock input."+ },+ {+ "number": "25",+ "name": "CAP3",+ "type": "output",+ "description": "Internally generated digital operating voltage that requires a 1-µF capacitor connected to DGND."+ },+ {+ "number": "26",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "27",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply that requires a 1-µF capacitor connected to DGND."+ },+ {+ "number": "28",+ "name": "RESET/PWDN",+ "type": "input",+ "description": "Active-low reset or power-down pin; see the Reset and Power-Down Pin section for hardware design details when using power-down mode."+ },+ {+ "number": "29",+ "name": "HR",+ "type": "input",+ "description": "ADC operating mode select: 1 = high-resolution (HR), 0 = low-power (LP) or very-low-power (VLP), with LP/VLP selected by the REXT resistor value."+ },+ {+ "number": "30",+ "name": "FORMAT",+ "type": "input",+ "description": "Interface select: 0 = SPI interface, 1 = frame-sync interface; hardware pin to be pulled high to DVDD or low to DGND through 100 kΩ."+ },+ {+ "number": "31",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "32",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply that must be decoupled to AGND with a 1-µF capacitor."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: LVDD is an analog-supply output when INTLDO=0 and an analog-supply input when INTLDO=1; typed as pow; CAP1, CAP2 and CAP3 are datasheet-labelled analog/digital output nodes meant for decoupling capacito; The datasheet describes FILTER[1:0] and OSR[1:0] as two-pin codes; each pin's description is the sha"+ ],+ "pages_sent": 12,+ "cost_usd": 0.09,+ "at": "2026-10-08T03:40:22"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads127l01",+ "pages": 90,+ "sha256": "7af2117fe188e693",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 32,+ "described": 32,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads127l01ipbsr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.96,+ 6.96,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b921f5b549adf0f328b9ae1afe19adae6a0c279f40fe06e1fcf119ac469aeffd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads127l01ipbsr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.96,+ 6.96,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "258fe577c68a66cd5ac3793d1fa7ca6428d6cfe4dabb0a91e82cbccfafcf7e7b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}