component
ADS124S08IPBS
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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+121@@ -0,0 +1,121 @@+# ADS124S08IPBS++**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-32(5x5)++ADS124S08IPBS from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AINCOM | passive | Common analog input for single-ended measurements. |+| 2 | AIN5 | passive | Analog input 5; absolute analog input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 3 | AIN4 | passive | Analog input 4; absolute analog input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 4 | AIN3 | passive | Analog input 3; absolute analog input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 5 | AIN2 | passive | Analog input 2; absolute analog input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 6 | AIN1 | passive | Analog input 1; absolute analog input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 7 | AIN0 | passive | Analog input 0; absolute analog input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 8 | START/SYNC | input | Start conversion; the rising edge of START/SYNC starts a new conversion, and digital inputs are limited to DGND - 0.3 V to IOVDD + 0.3 V. |+| 9 | CS | input | Active-low chip select; CS must be low for the entire data transaction, and when CS is high the serial interface resets and DOUT/DRDY goes high impedance. |+| 10 | DIN | input | Serial data input latched on the SCLK falling edge; keep DIN low during data readback when no command is intended. |+| 11 | SCLK | input | Serial clock input; a Schmidt-triggered input that latches DIN on the falling edge and must be returned low after the data sequence is complete. |+| 12 | DOUT/DRDY | tri_state | Serial data output combined with data ready, active low; the output is high impedance when CS is high. |+| 13 | DRDY | output | Active-low data-ready output that goes low to indicate conversion data are available for retrieval. |+| 14 | DGND | power_in | Digital ground. |+| 15 | IOVDD | power_in | Digital I/O power supply; if IOVDD is not tied to DVDD, connect a 100-nF (or larger) capacitor to DGND. |+| 16 | DVDD | power_in | Digital core power supply; connect a 100-nF (or larger) capacitor to DGND. |+| 17 | CLK | input | External clock input; connect to DGND to use the internal 4.096-MHz oscillator. |+| 18 | RESET | input | Active-low reset input. |+| 19 | GPIO3/AIN11 | bidirectional | General-purpose I/O 3 (logic levels based on the analog supply) or analog input 11; absolute voltage limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 20 | GPIO2/AIN10 | bidirectional | General-purpose I/O 2 (logic levels based on the analog supply) or analog input 10; absolute voltage limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 21 | GPIO1/AIN9 | bidirectional | General-purpose I/O 1 (logic levels based on the analog supply) or analog input 9; absolute voltage limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 22 | GPIO0/AIN8 | bidirectional | General-purpose I/O 0 (logic levels based on the analog supply) or analog input 8; absolute voltage limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 23 | REFOUT | power_out | Positive voltage reference output; connect a 1-µF to 47-µF capacitor to REFCOM when the internal voltage reference is enabled. |+| 24 | REFCOM | passive | Negative voltage reference output; connect to AVSS. |+| 25 | NC | unconnected | Leave unconnected or connect to AVSS. |+| 26 | AVDD | power_in | Positive analog power supply; connect a 330-nF (or larger) capacitor to AVSS. |+| 27 | AVSS | power_in | Negative analog power supply. |+| 28 | AVSS-SW | power_in | Negative analog power supply for the low-side switch; connect to AVSS. |+| 29 | REFN0 | passive | Negative external reference input 0; absolute input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V and continuous input current to ±100 mA. |+| 30 | REFP0 | passive | Positive external reference input 0; absolute input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 31 | REFN1/AIN7 | passive | Negative external reference input 1 or analog input 7 (ADS124S08 only); absolute input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |+| 32 | REFP1/AIN6 | passive | Positive external reference input 1 or analog input 6 (ADS124S08 only); absolute input voltage is limited to AVSS - 0.3 V to AVDD + 0.3 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-32(5x5) |+| Category | Data Acquisition |+| Pins | 32 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Power-supply voltage AVDD to AVSS | | -0.3 | | 5.5 | V | | 7 |+| AVSS to DGND | | -2.8 | | 0.3 | V | | 7 |+| DVDD to DGND | | -0.3 | | 3.9 | V | | 7 |+| IOVDD to DGND | | -0.3 | | 5.5 | V | | 7 |+| Continuous input current | | -100 | | 100 | mA | Continuous, AVSS-SW, REFN0, REFOUT | 7 |+| Continuous input current | | -10 | | 10 | mA | Continuous, all other pins except power-supply pins | 7 |+| Junction temperature | TJ | | | 150 | °C | Junction | 7 |+| Storage temperature | Tstg | -60 | | 150 | °C | Storage | 7 |+| Analog power supply AVDD to AVSS | | 2.7 | | 5.25 | V | | 8 |+| AVSS to DGND | | -2.625 | 0 | 0.05 | V | | 8 |+| AVDD to DGND | | 1.5 | | 5.25 | V | | 8 |+| Digital core power supply DVDD to DGND | | 2.7 | | 3.6 | V | | 8 |+| Digital IO power supply IOVDD to DGND | | | | 5.25 | V | | 8 |+| External clock frequency | fCLK | 2 | 4.096 | 4.5 | MHz | | 8 |+| External clock duty cycle | | 40 | 50 | 60 | % | | 8 |+| Operating ambient temperature | TA | -50 | | 125 | °C | | 8 |+| Differential reference input voltage | VREF | 0.5 | | | V | | 8 |+| Absolute input current, PGA enabled | | -2 | 0.1 | 2 | nA | PGA enabled, all gains, V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX | 9 |+| Differential input current, PGA enabled | | -1 | 0.02 | 1 | nA | PGA enabled, all gains, VCM = AVDD / 2, -VREF / Gain ≤ VIN ≤ VREF / Gain | 9 |+| Input offset voltage | VIO | -120 | 20 | 120 | µV | TA = 25°C, PGA bypassed | 9 |+| Input offset voltage | VIO | -15 | 2 | 15 | µV | TA = 25°C, PGA enabled, gain = 16 to 128 | 9 |+| Input offset voltage with global chop | VIO | -2 | 0.2 | 2 | µV | TA = 25°C, PGA bypassed, global chop enabled | 9 |+| Offset drift | | -75 | 10 | 75 | nV/°C | TA = -40°C to +85°C, PGA bypassed | 9 |+| Offset drift | | -100 | 15 | 100 | nV/°C | TA = -40°C to +85°C, PGA enabled, gain = 1 to 128 | 9 |+| Offset drift | | -200 | 15 | 200 | nV/°C | PGA enabled, gain = 1 to 8 | 9 |+| Offset drift | | -150 | 15 | 150 | nV/°C | PGA enabled, gain = 16 to 128 | 9 |+| Offset drift with global chop | | -10 | 2 | 10 | nV/°C | PGA bypassed, global chop enabled | 9 |+| Absolute input current, reference buffers disabled | | -6 | 4 | 6 | µA/V | Reference buffers disabled, external VREF = 2.5 V, REFP1/REFN1 inputs | 11 |+| Absolute input current, reference buffers enabled | | -15 | 5 | 15 | nA | Reference buffers enabled, external VREF = 2.5 V, REFP1/REFN1 inputs | 11 |+| Internal voltage reference accuracy | VREF | -0.05 | 0.01 | 0.05 | % | TA = 25°C, TQFP package | 11 |+| Output current | | -5 | | 5 | mA | AVDD = 2.7 V to 3.3 V, sink and source | 11 |+| Output current | | -10 | | 10 | mA | AVDD = 3.3 V to 5.25 V, sink and source | 11 |+| IDAC accuracy (each IDAC) | | -5 | 0.7 | 5 | % | TA = 25°C, 10 µA to 100 µA | 11 |+| IDAC accuracy (each IDAC) | | -3 | 0.5 | 3 | % | TA = 25°C, 250 µA to 2 mA | 11 |+| Internal oscillator accuracy | | -1.5 | | 1.5 | % | | 11 |+| Burnout current source accuracy | | -8 | | 8 | % | 0.2 µA, sinking or sourcing | 12 |+| Burnout current source accuracy | | -4 | | 4 | % | 1 µA, sinking or sourcing | 12 |+| Burnout current source accuracy | | -2 | | 2 | % | 10 µA, sinking or sourcing | 12 |+| Threshold 2 accuracy | | -3 | 1 | 3 | % | | 12 |+| Supply voltage monitor accuracy | | -1 | | 1 | % | (AVDD, AVSS) / 4 monitor | 12 |+| Input current, digital inputs | | -1 | | 1 | µA | DGND ≤ VDigital Input ≤ IOVDD | 12 |+| Junction-to-ambient thermal resistance | RθJA | | 75.5 | | °C/W | TQFP (PBS) package | 8 |+| Junction-to-case (top) thermal resistance | RθJC(top) | | 17.1 | | °C/W | TQFP (PBS) package | 8 |+| Junction-to-board thermal resistance | RθJB | | 28.5 | | °C/W | TQFP (PBS) package | 8 |+| Junction-to-top characterization parameter | ψJT | | 0.4 | | °C/W | TQFP (PBS) package | 8 |+| Junction-to-board characterization parameter | ψJB | | 28.3 | | °C/W | TQFP (PBS) package | 8 |++## CAD (KiCad official)++- Symbol: `ADS124S08IPBS`+- Footprint: `Package_QFP:TQFP-32_5x5mm_P0.5mm`+- 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm tall, family nominal (no datasheet A read)). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)+- 3D model files: `ads124s08ipbs-etched.step` / `ads124s08ipbs-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads124s08ipbs.step` / `ads124s08ipbs.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ads124s08.pdf) (115 pp, sha256 `38ac6914895f2c5b`, retrieved 2026-11-10, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads124s08ipbs-datasheet.pdf)
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],+ "rot": 0.0+ },+ {+ "number": "31",+ "shape": "roundrect",+ "center_mm": [+ -1.25,+ -3.1625+ ],+ "size_mm": [+ 0.3,+ 1.475+ ],+ "rot": 0.0+ },+ {+ "number": "32",+ "shape": "roundrect",+ "center_mm": [+ -1.75,+ -3.1625+ ],+ "size_mm": [+ 0.3,+ 1.475+ ],+ "rot": 0.0+ }+ ]+}
ads124s08ipbs.glbadded⋯ 1 unchanged line ⋯
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