component
ADS1231IDR
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# ADS1231IDR++**Texas Instruments** · Analog To Digital Converters (ADC) · SOIC-16++ADS1231IDR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DVDD | power_in | Digital power supply. 3 V to 5.3 V. Decouple to GND close to the pin. |+| 2 | GND | power_in | Ground for digital and analog supplies (shared with pin 11). |+| 3 | CLKIN | input | External clock input, typically 4.9152 MHz (1-6 MHz). Tie low to activate the internal oscillator. |+| 4 | SPEED | input | Data-rate select input. Logic 0 selects 10 SPS; logic 1 selects 80 SPS. |+| 5 | CAP | passive | Gain-amplifier bypass capacitor connection. Connect an external bypass capacitor between the two CAP pins (pins 5 and 6). |+| 6 | CAP | passive | Gain-amplifier bypass capacitor connection. Second terminal of the PGA bypass capacitor. |+| 7 | AINP | input | Positive analog input to the PGA/ADC. Common-mode range GND+1.5 V to AVDD-1.5 V; full-scale differential input +/-0.5*VREF/128. |+| 8 | AINN | input | Negative analog input to the PGA/ADC. Paired with AINP as the bridge-sensor differential input. |+| 9 | VREFN | input | Negative voltage reference input. Range GND-0.1 V to VREFP-1.5 V. |+| 10 | VREFP | input | Positive voltage reference input. Range VREFN+1.5 V to AVDD+0.1 V (external reference up to 5 V for ratiometric measurements). |+| 11 | GND | power_in | Ground for digital and analog supplies (shared with pin 2). |+| 12 | SW | output | Low-side power switch for the bridge sensor. Ron typ 3.5 ohm at AVDD=5V; max continuous switch current 30 mA. |+| 13 | AVDD | power_in | Analog power supply. 3 V to 5.3 V. Decouple to GND close to the pin. |+| 14 | PDWN | input | Power-down (active-low). Holding this pin low powers down the entire converter and resets the ADC. |+| 15 | SCLK | input | Serial clock: clocks out data on the rising edge. Also used to initiate Standby mode. Max 5 MHz. |+| 16 | DRDY/DOUT | output | Dual-purpose output. Data ready: indicates valid data by going low. Data output: outputs data MSB-first on the first rising edge of SCLK. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Data Acquisition |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `ADS1231IDR`++## CAD (KiCad official)++- Symbol: `ADS1231IDR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ads1231.pdf) (24 pp, sha256 `37a2ab763b8d0e7d`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads1231idr-datasheet.pdf)
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