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ADS1217IPFBR
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Texas Instruments Analog To Digital Converters (ADC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# ADS1217IPFBR++**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-48(7x7)++ADS1217IPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AVDD | power_in | Analog power supply input; the datasheet specifies AVDD at 4.75 V to 5.25 V for 5 V operation and 2.7 V to 3.3 V for 3 V operation. |+| 2 | AGND | power_in | Analog ground return for the analog circuitry. |+| 3 | AIN0 | passive | Analog input channel 0 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 4 | AIN1 | passive | Analog input channel 1 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 5 | AIN2 | passive | Analog input channel 2 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 6 | AIN3 | passive | Analog input channel 3 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 7 | AIN4 | passive | Analog input channel 4 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 8 | AIN5 | passive | Analog input channel 5 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 9 | AIN6 | passive | Analog input channel 6 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 10 | AIN7 | passive | Analog input channel 7 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V. |+| 11 | AINCOM | passive | Analog input common connection for the multiplexed analog inputs. |+| 12 | AGND | power_in | Analog ground return for the analog circuitry. |+| 13 | AVDD | power_in | Analog power supply input; the datasheet specifies AVDD at 4.75 V to 5.25 V for 5 V operation and 2.7 V to 3.3 V for 3 V operation. |+| 14 | VRCAP | passive | Bypass capacitor connection for the on-chip VREFOUT reference. |+| 15 | IDAC1 | output | Current DAC 1 output; the full-scale current is set by the RDAC resistor (0.5 mA to 2 mA at RDAC = 150 kΩ, per range). |+| 16 | IDAC2 | output | Current DAC 2 output; the full-scale current is set by the RDAC resistor (0.5 mA to 2 mA at RDAC = 150 kΩ, per range). |+| 17 | RDAC | passive | Current DAC setting resistor connection; the datasheet specifies RDAC between 10 kΩ and the value used to set the IDAC full-scale current. |+| 18 | DGND | power_in | Digital ground return for the digital circuitry. |+| 19 | DGND | power_in | Digital ground return for the digital circuitry. |+| 20 | DGND | power_in | Digital ground return for the digital circuitry. |+| 21 | DGND | power_in | Digital ground return for the digital circuitry. |+| 22 | DGND | power_in | Digital ground return for the digital circuitry. |+| 23 | BUFEN | input | Buffer enable input that selects the high-input-impedance analog input buffer. |+| 24 | RESET | input | Active LOW input that resets the entire chip. |+| 25 | XIN | input | Clock input for the master clock (crystal or resonator, or external clock; master clock range 1 MHz to 8 MHz). |+| 26 | XOUT | output | Clock output used with a crystal or resonator. |+| 27 | PDWN | input | Active LOW power-down input that shuts down the analog and digital circuits. |+| 28 | POL | input | Serial clock polarity input for the SPI interface. |+| 29 | DSYNC | input | Active LOW synchronization control input. |+| 30 | DGND | power_in | Digital ground return for the digital circuitry. |+| 31 | DVDD | power_in | Digital power supply input; the datasheet specifies DVDD from 2.7 V to 5.25 V. |+| 32 | DRDY | output | Active LOW data ready output that indicates a new conversion result is available. |+| 33 | CS | input | Active LOW chip select input for the serial interface (may be tied LOW). |+| 34 | SCLK | input | Serial clock input with Schmitt-trigger input; SCLK pulse width HIGH and LOW must be at least 200 ns. |+| 35 | DIN | input | Serial data input with Schmitt-trigger input; data must be set up and held around the SCLK edge (50 ns minimum each). |+| 36 | DOUT | output | Serial data output; goes tri-state immediately when CS goes HIGH. |+| 37 | D0 | bidirectional | Digital I/O bit 0, usable as input or output. |+| 38 | D1 | bidirectional | Digital I/O bit 1, usable as input or output. |+| 39 | D2 | bidirectional | Digital I/O bit 2, usable as input or output. |+| 40 | D3 | bidirectional | Digital I/O bit 3, usable as input or output. |+| 41 | D4 | bidirectional | Digital I/O bit 4, usable as input or output. |+| 42 | D5 | bidirectional | Digital I/O bit 5, usable as input or output. |+| 43 | D6 | bidirectional | Digital I/O bit 6, usable as input or output. |+| 44 | D7 | bidirectional | Digital I/O bit 7, usable as input or output. |+| 45 | AGND | power_in | Analog ground return for the analog circuitry. |+| 46 | VREFOUT | output | On-chip voltage reference output (1.25 V or 2.5 V, selected by REF HI). |+| 47 | VREF+ | power_in | Positive differential reference input; the reference input VREF (VREF+ minus VREF-) is specified from 0.1 V to 2.6 V. |+| 48 | VREF- | power_in | Negative differential reference input; specified from AGND - 0.1 V to (VREF+) - 0.1 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-48(7x7) |+| Category | Data Acquisition |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `ADS1217IPFBR`+- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`+- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `ads1217ipfbr-etched.step` / `ads1217ipfbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads1217ipfbr.step` / `ads1217ipfbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads1217) (33 pp, sha256 `0a2b6af4651a91dd`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads1217ipfbr-datasheet.pdf)
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the datasheet specifies AVDD at 4.75 V to 5.25 V for 5 V operation and 2.7 V to 3.3 V for 3 V operation."+ },+ {+ "number": "2",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return for the analog circuitry."+ },+ {+ "number": "3",+ "name": "AIN0",+ "type": "passive",+ "description": "Analog input channel 0 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "4",+ "name": "AIN1",+ "type": "passive",+ "description": "Analog input channel 1 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "5",+ "name": "AIN2",+ "type": "passive",+ "description": "Analog input channel 2 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "6",+ "name": "AIN3",+ "type": "passive",+ "description": "Analog input channel 3 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "7",+ "name": "AIN4",+ "type": "passive",+ "description": "Analog input channel 4 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "8",+ "name": "AIN5",+ "type": "passive",+ "description": "Analog input channel 5 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "9",+ "name": "AIN6",+ "type": "passive",+ "description": "Analog input channel 6 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "10",+ "name": "AIN7",+ "type": "passive",+ "description": "Analog input channel 7 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V."+ },+ {+ "number": "11",+ "name": "AINCOM",+ "type": "passive",+ "description": "Analog input common connection for the multiplexed analog inputs."+ },+ {+ "number": "12",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return for the analog circuitry."+ },+ {+ "number": "13",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply input; the datasheet specifies AVDD at 4.75 V to 5.25 V for 5 V operation and 2.7 V to 3.3 V for 3 V operation."+ },+ {+ "number": "14",+ "name": "VRCAP",+ "type": "passive",+ "description": "Bypass capacitor connection for the on-chip VREFOUT reference."+ },+ {+ "number": "15",+ "name": "IDAC1",+ "type": "output",+ "description": "Current DAC 1 output; the full-scale current is set by the RDAC resistor (0.5 mA to 2 mA at RDAC = 150 kΩ, per range)."+ },+ {+ "number": "16",+ "name": "IDAC2",+ "type": "output",+ "description": "Current DAC 2 output; the full-scale current is set by the RDAC resistor (0.5 mA to 2 mA at RDAC = 150 kΩ, per range)."+ },+ {+ "number": "17",+ "name": "RDAC",+ "type": "passive",+ "description": "Current DAC setting resistor connection; the datasheet specifies RDAC between 10 kΩ and the value used to set the IDAC full-scale current."+ },+ {+ "number": "18",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return for the digital circuitry."+ },+ {+ "number": "19",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return for the digital circuitry."+ },+ {+ "number": "20",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return for the digital circuitry."+ },+ {+ "number": "21",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return for the digital circuitry."+ },+ {+ "number": "22",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return for the digital circuitry."+ },+ {+ "number": "23",+ "name": "BUFEN",+ "type": "input",+ "description": "Buffer enable input that selects the high-input-impedance analog input buffer."+ },+ {+ "number": "24",+ "name": "RESET",+ "type": "input",+ "description": "Active LOW input that resets the entire chip."+ },+ {+ "number": "25",+ "name": "XIN",+ "type": "input",+ "description": "Clock input for the master clock (crystal or resonator, or external clock; master clock range 1 MHz to 8 MHz)."+ },+ {+ "number": "26",+ "name": "XOUT",+ "type": "output",+ "description": "Clock output used with a crystal or resonator."+ },+ {+ "number": "27",+ "name": "PDWN",+ "type": "input",+ "description": "Active LOW power-down input that shuts down the analog and digital circuits."+ },+ {+ "number": "28",+ "name": "POL",+ "type": "input",+ "description": "Serial clock polarity input for the SPI interface."+ },+ {+ "number": "29",+ "name": "DSYNC",+ "type": "input",+ "description": "Active LOW synchronization control input."+ },+ {+ "number": "30",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return for the digital circuitry."+ },+ {+ "number": "31",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply input; the datasheet specifies DVDD from 2.7 V to 5.25 V."+ },+ {+ "number": "32",+ "name": "DRDY",+ "type": "output",+ "description": "Active LOW data ready output that indicates a new conversion result is available."+ },+ {+ "number": "33",+ "name": "CS",+ "type": "input",+ "description": "Active LOW chip select input for the serial interface (may be tied LOW)."+ },+ {+ "number": "34",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input with Schmitt-trigger input; SCLK pulse width HIGH and LOW must be at least 200 ns."+ },+ {+ "number": "35",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input with Schmitt-trigger input; data must be set up and held around the SCLK edge (50 ns minimum each)."+ },+ {+ "number": "36",+ "name": "DOUT",+ "type": "output",+ "description": "Serial data output; goes tri-state immediately when CS goes HIGH."+ },+ {+ "number": "37",+ "name": "D0",+ "type": "bidirectional",+ "description": "Digital I/O bit 0, usable as input or output."+ },+ {+ "number": "38",+ "name": "D1",+ "type": "bidirectional",+ "description": "Digital I/O bit 1, usable as input or output."+ },+ {+ "number": "39",+ "name": "D2",+ "type": "bidirectional",+ "description": "Digital I/O bit 2, usable as input or output."+ },+ {+ "number": "40",+ "name": "D3",+ "type": "bidirectional",+ "description": "Digital I/O bit 3, usable as input or output."+ },+ {+ "number": "41",+ "name": "D4",+ "type": "bidirectional",+ "description": "Digital I/O bit 4, usable as input or output."+ },+ {+ "number": "42",+ "name": "D5",+ "type": "bidirectional",+ "description": "Digital I/O bit 5, usable as input or output."+ },+ {+ "number": "43",+ "name": "D6",+ "type": "bidirectional",+ "description": "Digital I/O bit 6, usable as input or output."+ },+ {+ "number": "44",+ "name": "D7",+ "type": "bidirectional",+ "description": "Digital I/O bit 7, usable as input or output."+ },+ {+ "number": "45",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return for the analog circuitry."+ },+ {+ "number": "46",+ "name": "VREFOUT",+ "type": "output",+ "description": "On-chip voltage reference output (1.25 V or 2.5 V, selected by REF HI)."+ },+ {+ "number": "47",+ "name": "VREF+",+ "type": "power_in",+ "description": "Positive differential reference input; the reference input VREF (VREF+ minus VREF-) is specified from 0.1 V to 2.6 V."+ },+ {+ "number": "48",+ "name": "VREF–",+ "type": "power_in",+ "description": "Negative differential reference input; specified from AGND - 0.1 V to (VREF+) - 0.1 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 14 is printed as 'VRCAP VREFOUT Bypass Capacitor' in the pin description table and 'VRCAP' in th; Pin descriptions for DGND (18-22) and D0-D7 (37-44) were expanded per pin from the range rows in the; Pin descriptions for IDAC1, IDAC2, RDAC, VREF+/VREF-, and the analog inputs carry numeric limits tak"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0803,+ "at": "2026-10-08T18:32:53"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads1217",+ "pages": 33,+ "sha256": "0a2b6af4651a91dd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads1217ipfbr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "14ca7676e4932e92f0eca0c6d56ce3018cd28a2531204a70ab7bbacb3eeb3cf5",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads1217ipfbr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b48b29da3dbec7302f0205566c115a9b9d7cc3ab18d4ad45593c08a1dbec018d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}