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Record drill-void model defect and keep copper acceptance open

John Lauer ·dc834fa648 ·16d ago ·parent d9647fc
3 files changed +69−1
design/hotspot-v18-review.json+9−1
@@ -18,7 +18,15 @@     "DUT_FUSED": 45.40793228149414,     "5V_AUX": 18.182907104492188   },-  "fineMesh": "0.1 mm solve in progress",+  "fineMesh": {+    "cellMm": 0.1,+    "unclippedCurrentPeaks": {+      "GND": 102.23749542236328,+      "LOAD_POS": 63.24799346923828,+      "SHUNT_P": 78.4032211303711+    },+    "finding": "Worst coordinates lie inside via drills. Raster paints solid discs and vertical conductance is concentrated at center cell. Source correction under development; neither mesh accepted."+  },   "thermalAttributionOnly": {     "note": "Q1 loss omitted to isolate diode/shunt board heating; not an operating case or thermal acceptance",     "parts": [
design/plated-hole-model-discovery.jsonadded+54
@@ -0,0 +1,54 @@+{+  "board": "checkpoints/unclipped-hotspots-v1/candidate-v18.kicad_pcb",+  "meshMm": 0.1,+  "status": "Model defect reproduced; no copper acceptance",+  "findings": [+    {+      "net": "LOAD_POS",+      "peakJ": 63.24799346923828,+      "peakAt": [+        126.05,+        86.85000000000001+      ],+      "holes": []+    },+    {+      "net": "GND",+      "peakJ": 102.23749542236328,+      "peakAt": [+        136.45000000000002,+        93.05+      ],+      "holes": [+        {+          "via": "af11e84f-6d71-4241-89be-0a1feefd7721",+          "at": [+            136.5,+            93.0+          ],+          "drillMm": 0.6,+          "peakCellEntirelyInsideDrill": true+        }+      ]+    },+    {+      "net": "SHUNT_P",+      "peakJ": 78.4032211303711,+      "peakAt": [+        133.75,+        84.25+      ],+      "holes": [+        {+          "via": "aa6c5964-74d4-410e-a69e-ffb2cd9c9999",+          "at": [+            133.8,+            84.2+          ],+          "drillMm": 0.6,+          "peakCellEntirelyInsideDrill": true+        }+      ]+    }+  ]+}
docs/completion-plan.md+6
@@ -1,3 +1,9 @@+## Current checkpoint — plated-hole model correction++Do not execute the v18 landing plan. The 0.1 mm refinement produced GND 102.24, drain 63.25 and shunt 78.40 A/mm². The complete GND and shunt peak cells lie inside drilled holes: the old raster painted solid discs and coupled layers at their centers. An isolated Fields correction removes drill voids and distributes wall coupling, with 32 passing tests and a production build. Its v18 rerun still fails real surface screens (GND 71.93 and shunt 89.36 at 0.2 mm); the fix does not manufacture a passing result. Barrel currents are now reported separately.++Candidate v21 preserves the three dedicated shunt thermal vias, removes two intermediate power vias that constrain in-plane copper, and restores smaller drills in two narrow paths. Native net invariants and DRC pass (zero errors/opens, 15 inherited warnings); its corrected-field solve is running. Neither candidate is landed. Fields source remains under owner review; installed shared Fields is unchanged.+ ## Active checkpoint — unclipped current rework v18  The isolated candidate passes native net-intent invariants, DRC (zero errors and opens; 15 inherited library warnings), and the six-net 0.2 mm current screen. Ground 58.70, drain 57.30 and shunt 59.33 A/mm² remain below the unchanged 60 threshold at this mesh only. A 0.1 mm three-net refinement is running. The live PCB is unchanged. No current or thermal gate is marked passed.