Adom Custom Electronic Load

@@ -0,0 +1,5 @@+OK: heatsink via plan (0 vias): aiflow/run/plan-thermal-vias.json+  D1    LOAD_POS target 10  existing 10  planned  0+  Q1    LOAD_POS target 16  existing  0  planned  0  (room for 0 of 16 vias within 3 mm of Q1 and inside both planned LOAD_POS copper regions: review local copper and cooling; native refill/connectivity still required)+  RSH1  SHUNT_P target  6  existing  3  planned  0  (room for 3 of 6 vias within 3 mm of RSH1 and inside both planned SHUNT_P copper regions: review local copper and cooling; native refill/connectivity still required)+Hint: Review it with the human in one line per part, then `thermal-vias land`. A part with a note needs your call: pour its net on the other layer, move a neighbour, or `--ack REF --why`.

@@ -4,7 +4,9 @@ The active objective is to finish this electronic-load design through AIFlow, th  ## Latest accepted board -Native-saved board 17 SHA-256 `653e54e711552eb2f16b6d01cd144fd82645a52c30ff11e39699b760402af51a`. D1 rotation, parallel power paths, back-source expansion and a further shunt via are landed. Native DRC has zero errors/opens; saved physical copper matches the checked candidate. Explicit-terminal SHUNT_P peaks are 57.9 A/mm² at 0.2 mm mesh and 59.4 at 0.1 mm; all five reviewed nets are below 60 in this experimental diagnostic, with a small margin. Formal current/thermal gates and assembly cooling remain incomplete. Read shunt-final-review.md. Output-locked STM32 USB/tach bring-up compiles and host tests pass; hardware remains unflashed and unverified.+Native-saved board 18 SHA-256 `8d6cd24149f7de061f125bf45a26b50ca5b70a6b01c62b96dc3cf92187a531f1`. Nine D1 thermal vias were added to board 17, recorded and saved. Native DRC has zero errors/opens and 15 inherited library warnings. AIFlow adopted the saved board, re-ran routing and gate, and recorded the empty routing plan as landed. D1 now has 10 of 10 planned thermal vias. Six added-via coordinates differ from the offline generator by at most one nanometre per axis; read the explicit rounding audit. The earlier candidate current screen is diagnostic evidence, not a new formal same-board Fields pass. Both native 2D and 3D views and the published 2x video were inspected. Output-locked STM32 bring-up remains unflashed and unqualified.++Installed Fields remains 0.6.2; physical two-layer/plated-pad PR 5 is still open. Its rectangular heat blocks contact the PCB face, not the MOSFET case. Do not substitute that model for the missing package/interface/sink/airflow analysis. The four-hole 40 mm sink pattern was rejected against routed copper. Investigate the existing Q1 3.5 mm mounting hole at (127.46,65.34), with actual hardware, electrical isolation and support rather than assuming it qualifies an assembly.  ## Resume here