Adom Custom Electronic Load

@@ -2,7 +2,7 @@  **R0 engineering prototype — not released for fabrication.** A digitally controlled, fan-cooled constant-current load designed as an Adom molecule for the probing workcell. -The provisional target is 25 W, 24 V and 3 A with simultaneous limits; the first acceptance DUT is the 12 V-to-5 V, 1 A buck molecule. The lower-cost pass transistor targets 5–24 V loading. USB CDC is the preferred control-panel link, with 3.3 V UART contacts for future automated wiring. Auxiliary 5 V powers the fan and logic independently of the DUT.+The compact R0 prototype target is 5 W, 24 V and 3 A with simultaneous limits; the first acceptance DUT is the 12 V-to-5 V, 1 A buck molecule. The lower-cost pass transistor targets 5–24 V loading. USB CDC is the preferred control-panel link, with 3.3 V UART contacts for future automated wiring. Auxiliary 5 V powers the fan and logic independently of the DUT.  The architecture uses an IXTP15N50L2 linear MOSFET, four-terminal 20 mΩ shunt, OPA189 servo, DAC60501 setpoint, INA226 telemetry and STM32G0B1 supervisor. Hardware comparators, an asynchronous fault latch and an external watchdog hold the gate off on faults. Cooling and the complete measurement error budget remain under review. @@ -13,7 +13,7 @@ The architecture uses an IXTP15N50L2 linear MOSFET, four-terminal 20 mΩ shunt, - The portable C safety-policy core passes host tests. Flashable MCU firmware and USB integration are not complete. - The saved two-layer routed board has zero native DRC errors and zero unconnected nets, with zero warnings in the latest saved-board check. Twelve power-track segments were widened and a parallel shunt via added after isolated checks; see the [power-width review](docs/power-width-review.md) and [shunt-path review](docs/shunt-path-review.md). All nine planned measurements have probe access, including dedicated fan-tach and Kelvin-minus pads. Current/thermal, USB, cooling and fabrication qualification remain incomplete. - The fan has a [component page with GLB motion states](https://wiki.adom.inc/adom/mf40200v1-1000u-g99). Its preview is simulated; shared viewer integration remains proposed.-- The [thermal budget](docs/thermal-budget.md) now matches the 55 °C firmware trip ceiling. The 25 W target is not validated; bring-up remains capped at 5 W.+- The [thermal budget](docs/thermal-budget.md) now matches the 55 °C firmware trip ceiling. The earlier 25 W assumption is retained as an unqualified future option; R0 targets 5 W and still requires cooling validation. - Build footage is being collected. Failed/static captures are identified in the shot log rather than included as action footage.  Read the [engineering status](docs/status.md), [placement review](docs/placement-review.md), [library review](docs/library-review.md), [cost breakdown](docs/cost/README.md), [firmware/control-panel contract](docs/firmware-contract.md), and [raw clip log](videos/shotlog.json). The [AI Flow report](docs/runs/board-codex-20261007-1749/README.md) records the run.

@@ -3,8 +3,8 @@   "envelope": {     "max_V": 24,     "max_A": 3,-    "max_W": 25,-    "I_at_max_V_A": 1.0416666666666667+    "max_W": 5,+    "I_at_max_V_A": 0.20833333333333334   },   "shunt": {     "ohm": 0.02,@@ -32,8 +32,8 @@     "case_limit_C": 55,     "interface_assumed_C_W": 0.5,     "thetaJC_max_C_W": 0.42,-    "allowable_sink_C_W": 0.09999999999999998,-    "junction_C_at_case_limit": 65.5,+    "allowable_sink_C_W": 2.5,+    "junction_C_at_case_limit": 57.1,     "bringup_W": 5,     "bringup_allowable_sink_C_W": 2.5,     "note": "55 C is the firmware trip ceiling, not a continuous operating target; tolerance, sensor lag and margin require lower temperatures. Worst-case all load power placed in MOSFET; interface is an assumption, must verify actual insulator and spreading. Fan free-air CFM is not installed airflow."

@@ -0,0 +1,21 @@+{+  "version": "0.1.76",+  "sourceCommit": "7c20faf34a201409926758f82a8e3978fc8fc02d",+  "installedVerified": true,+  "changes": [+    "Original requested scope remains active after supporting tasks",+    "Optional working assumptions must not become artificial blockers",+    "done ends session accounting only",+    "No automatic host restart claimed"+  ],+  "validation": [+    "Cargo workspace tests pass",+    "Production release build passes",+    "149-reference component workflow passes",+    "Widget workflow passes",+    "Silkscreen geometry tests pass",+    "CLI commands preserved; only done help changed",+    "Immutable HEAD preflight passes"+  ],+  "boardContinuation": "Compact 5 W basis recorded; thermal/mechanical review underway; no finish claim"+}

@@ -124,10 +124,10 @@   },   "hot": {     "Q1": {-      "watts": 25,+      "watts": 5,       "tabNet": "LOAD_POS",       "maxRiseC": 15,-      "note": "25 W design-target screen against the 55 C firmware case trip at assumed 40 C ambient. External heatsink unresolved; board-only solver cannot validate cooling."+      "note": "Compact R0 5 W prototype target; 55 C case trip at assumed 40 C ambient unchanged. External heatsink remains required and unresolved; board-only solver is not cooling qualification."     },     "D1": {       "watts": 1.65,@@ -337,7 +337,7 @@     "calcs",     "simulation"   ],-  "qualificationNote": "Limits are simultaneous. MOSFET25W plus diode/shunt losses are conservative separate layout screens, not one physical operating point. Heatsink contact, mounted airflow, USB impedance, contact current ratings and prototype tests remain unverified.",+  "qualificationNote": "Simultaneous 5 W/24 V/3 A limits; 3 A conductor, diode and shunt screens retained conservatively although initial DUT is 5 V/1 A. 25 W is a future option, not R0 rating. Actual cooling, USB and contact ratings remain unverified.",   "planes": {     "GND": "B.Cu"   },

@@ -3,7 +3,7 @@ Design in progress; no PCB or fabrication release yet.  ## Proposed envelope-25 W continuous, 24 V maximum and 3 A maximum, simultaneously constrained. Initial DUT is the TPS54202 5 V / 1 A buck molecule. Ambient target 0–40 C is provisional. Cooling must establish the actual derating curve. Current setting target is 1 mA increments; calibrated accuracy target ±(0.2% reading + 1 mA), subject to full error budget and bench verification. These are design targets, not achieved specifications.+5 W compact R0 prototype target, 24 V maximum and 3 A maximum, simultaneously constrained. Initial DUT is the TPS54202 5 V / 1 A buck molecule. Ambient target 0–40 C is provisional. Cooling must establish the actual derating curve. Current setting target is 1 mA increments; calibrated accuracy target ±(0.2% reading + 1 mA), subject to full error budget and bench verification. These are design targets, not achieved specifications.  ## Power and control DUT+ -> fuse / reverse-protection path -> linear MOSFET -> four-terminal low-side shunt -> DUT-. An analog op-amp loop controls shunt voltage from a precision DAC. MCU supervises setpoints and measures voltage/current; the analog loop controls current continuously. USB CDC is primary, a 3.3 V UART is provisioned on machine contacts for future automatic wiring. Do not route USB D+/D- as arbitrary pincer wires.@@ -27,3 +27,5 @@ AIFlow loaded adom-3rdpartyfab-2L: 1.6 mm board, 1 oz copper. Apply conservative  ## Evidence boundaries Research and a public datasheet-review clip are captured. Native KiCad 10 and shared service are available. Fusion app-state query timed out; no existing document was changed. AIFlow pre-board timeline is open, but its ordered KiCad steps require component/library/model proofs before the test-plan step. Design work is tracked as an explicit design stage; no gate has been bypassed.++The 25 W envelope was an earlier assistant assumption and remains an unqualified future option. Selecting the 5 W prototype target follows the original compact/low-cost brief and initial DUT; it does not waive thermal validation or relax the shutdown policy.

@@ -9,7 +9,7 @@ AIFlow board-11, native-saved SHA-256 `e5e3e2f007d13fe6bd54e0dd5a27de18f5c87dab5 ## Resume here  1. Inspect the live AdomLapper board and AIFlow run; current required step is thermal-vias. Preserve other threads and project rules.-2. Resolve the pending user product choice: compact 5 W design versus 25 W with larger cooling. The 25 W value was an assistant assumption. Do not silently alter it or raise the 55 C shutdown limit. Existing 5 W bring-up policy is not qualification.+2. Continue the compact 5 W prototype basis announced on 9 October. It follows the original size/cost priority and 5 V/1 A DUT. The prior 25 W assistant assumption is documented as a future option, not a blocker. Keep the 55 C trip and all validation requirements. 3. Solve the actual MOSFET case/interface/sink/fan assembly and probe clearance. Rejected shunt-via candidates disconnected ground; do not replay them. Via-count acknowledgements require actual engineering justification, not a desire to advance the timeline. 4. Complete and revalidate pours, outline, same-board current/thermal Fields screens, net tour, full fitted-model/silkscreen review, native 3D, finish and fabrication exports in the enforced sequence. Record significant real actions. Never mark these passed to bypass an unresolved gate. 5. Complete firmware/HAL/USB integration and control-panel behavior, full component/provenance review, molecule assets, cost/BOM coverage and wiki delivery. Label hardware-dependent calibration, airflow, fan-stall and thermal qualification explicitly unverified until tested.

@@ -0,0 +1,7 @@+# Continuation correction — 9 October 2026++AIFlow 0.1.76 changes the main skill and prompt/`done` CLI guidance to preserve the original requested scope across supporting work. Status updates, dashboard edits and tool repairs lead back to the next engineering action. Reversible choices use the user’s priorities and explicit working assumptions; they do not automatically become blocking questions. Required ratings, safety limits and evidence gates remain intact.++Source commit `7c20faf34a201409926758f82a8e3978fc8fc02d`, registry publication and installed 0.1.76 were verified separately. Cargo workspace tests, production build, the 149-reference component workflow, widget checks and silkscreen geometry checks passed. CLI commands are preserved; only `done` help changed. This is guidance for the AI, not an automatic host restart mechanism.++The electronic load proceeds on the compact 5 W prototype basis for its initial 5 V/1 A DUT. The earlier 25 W assumption remains an unqualified future option. Cooling candidates remain isolated until native acceptance; moving the fan connector and two probe pads creates room for an offset 50 mm cooling envelope. Full cooling qualification remains open.

@@ -10,7 +10,7 @@ Every boot starts disabled: configure MCU_ENABLE low and ARM_CLK low before peri  The 1.6 s nominal external watchdog has a 1.12–2.24 s specified timeout. Firmware toggles WDI only after a complete healthy control cycle, never from an unconditional timer interrupt. The independent comparator/latch chain handles case-sensor open/short, overtemperature, overcurrent and overvoltage. The software host lease is 1 s; sensor age limit 50 ms. These timings require hardware acceptance tests. -The policy core starts with a **5 W bring-up ceiling**, 3 A maximum, 24 V maximum and 1 A/s upward slew. Raising the ceiling toward the 25 W design target requires verified cooling and assembly qualification. The `assembly_qualified` input is a trusted build/calibration configuration, not a serial command. Upward steps are limited; downward power limiting is immediate. Fan tach timeout and thermistor thresholds are provisional and must be confirmed against the assembled fan/sensor.+The policy core starts with a **5 W bring-up ceiling**, 3 A maximum, 24 V maximum and 1 A/s upward slew. The compact R0 design target is also 5 W. Any future higher-power revision requires verified cooling and assembly qualification. The `assembly_qualified` input is a trusted build/calibration configuration, not a serial command. Upward steps are limited; downward power limiting is immediate. Fan tach timeout and thermistor thresholds are provisional and must be confirmed against the assembled fan/sensor.  Telemetry should include DUT voltage/current/power, case temperature, tach RPM, DAC code, requested/applied current, state, latched faults, firmware revision, calibration ID, sample timestamp and link status. Measured power is `V*I`; input/output buck efficiency requires a separate input-side measurement. USB and UART share the same state machine and cannot independently own the load. 

@@ -2,7 +2,7 @@  The saved two-layer board now has 104 footprints, 52 nets, 1,668 track segments and 256 vias. Native KiCad reports **zero DRC errors and zero unconnected items**. Fifteen library-configuration warnings remain in the validation snapshot; these are not a complete library qualification. U10 is inline near the USB connector; R31/R32 are 0-ohm links, matching the STM32G0B1 internal-termination requirement. The intended 52-net schematic check passes. Unused USB power, fan tach and SWCLK trace ends were removed. -AIFlow adopted this native-saved revision as board-11 and returned to routing to regenerate its dependent proofs. Cooling, current/thermal screening, final model and silkscreen review, firmware integration and fabrication release remain unfinished. The 5 W bring-up limit remains; the provisional 25 W target is not validated. No hardware has been built or qualified.+AIFlow adopted this native-saved revision as board-11 and returned to routing to regenerate its dependent proofs. Cooling, current/thermal screening, final model and silkscreen review, firmware integration and fabrication release remain unfinished. The compact R0 working target is 5 W, consistent with the original size/cost priority and initial DUT; 25 W remains an unqualified future option. No hardware has been built or qualified.  There are 42 indexed raw takes and 16 previously reviewed excerpts; two new raw takes show actual USB footprint/copper edits and trace-stub cleanup. The final narrated film is unfinished. 

@@ -1,3 +1,7 @@+# Current R0 basis — 2026-10-09++Proceed with the compact 5 W prototype target for the initial 5 V/1 A DUT. The earlier 25 W envelope was an assistant assumption and is now a future option. The 55 C trip and 40 C ambient screening assumptions remain unchanged. This choice does not establish an operating rating or waive the actual cooling checks.+ # Thermal budget correction — 2026-10-08  The 25 W envelope is a design target, not an established continuous rating. The initial calculation assumed a 75 °C MOSFET case while the portable firmware trips at 55 °C. Those assumptions were inconsistent. The calculation now uses 55 °C as an upper ceiling; normal operation must remain below it with allowance for tolerances, sensor lag and temperature gradients.

@@ -0,0 +1,77 @@+{+  "boardSha256": "e5e3e2f007d13fe6bd54e0dd5a27de18f5c87dab56c4034c3b58935c0b0e6e87",+  "basis": "Nominal 50 x 50 x 10 mm sink and 40 x 40 x 20 mm fan; no assembly accepted",+  "nominalStackMmAboveBoard": 34.655,+  "notIncluded": [+    "height tolerance",+    "fan guard",+    "mounting hardware",+    "wire bends",+    "installed airflow",+    "case interface/spreading resistance"+  ],+  "headerBoundsMm": {+    "J9": [+      152.73,+      73.73,+      160.35,+      76.27+    ],+    "J10": [+      102.73,+      71.73,+      107.81,+      74.27+    ]+  },+  "candidates": [+    {+      "name": "Centered 50 mm sink",+      "box": [+        102.46,+        46,+        152.46,+        96+      ],+      "probeKeepoutRadiusMm": 2,+      "probeConflicts": [+        "TP13",+        "TP11",+        "TP6",+        "TP7",+        "TP4",+        "TP3",+        "TP2",+        "TP1",+        "TP9",+        "TP5",+        "TP10",+        "TP8",+        "TP12"+      ],+      "headerConflicts": [+        "J10"+      ],+      "accepted": false+    },+    {+      "name": "Offset 50 mm sink",+      "box": [+        112,+        35,+        162,+        85+      ],+      "probeKeepoutRadiusMm": 2,+      "probeConflicts": [+        "TP4",+        "TP8"+      ],+      "headerConflicts": [+        "J9"+      ],+      "accepted": false+    }+  ],+  "nextAction": "Offset candidate moves TP4 to (100.8,77.2), TP8 to (100.8,80), J9 to (154.6,98), rotation -90; native routing and full fitted-body acceptance remain required."+}

@@ -0,0 +1,20 @@+{+  "mpn": "ATS-CPX050050010-121-C1-R0",+  "status": "candidate, not selected qualified assembly",+  "source": "https://www.qats.com/Search/HeatSink/2874.aspx",+  "datasheet": "https://www.qats.com/DataSheet/ATS-CPX050050010-121-C1-R0",+  "dimensionsMm": [+    50,+    50,+    10+  ],+  "mountingHolePitchMm": [+    43,+    43+  ],+  "material": "AL6063",+  "timIncluded": false,+  "cadAccess": "Manufacturer technical table offers STEP via Login.aspx; no CAD downloaded or redistribution permission established",+  "retrieved": "2026-10-09",+  "browserRecovery": "Direct HTTP request returned 403; Pup successfully rendered manufacturer product and technical table; recorded."+}

@@ -20,9 +20,9 @@         24       ],       "I_max_A": 3,-      "P_continuous_W": 25,+      "P_continuous_W": 5,       "assumed": true,-      "why": "Proposed envelope pending user response; simultaneous limits apply",+      "why": "Working prototype target selected from user compact/low-cost priority, initial 5 V/1 A DUT and existing 5 W bring-up policy; not a measured rating.",       "compliance_note": "Voltage measurement range 0-24 V does not imply full current at 0 V. Lower-cost IXTP15N50L2 build targets 5-24 V loading; IXTP64N10L2 retained as pin-compatible low-voltage candidate pending measured compliance."     }   ],@@ -73,5 +73,12 @@     "Existing 5V 1A buck is initial acceptance DUT",     "Exact copper and fabrication limits must come from selected rule pack",     "Auxiliary 5 V is supplied by control-panel PS2; USB is data-only. No isolation."+  ],+  "futureOptions": [+    {+      "P_continuous_W": 25,+      "status": "unqualified higher-power option; not required for compact R0",+      "origin": "earlier assistant assumption"+    }   ]-}\ No newline at end of file+}

@@ -0,0 +1,23 @@+"""Screen nominal XY cooling envelopes against actual probe centers and tall connectors.+This is a conservative planning view, not a mechanical or thermal acceptance check.+"""+from pathlib import Path+import sys,json,math,hashlib+sys.path.insert(0,str(Path(__file__).parent));import sexp+p=Path(__file__).resolve().parents[1];board=p/'kicad/adom-custom-electronic-load.kicad_pcb'+b=sexp.parse(board.read_text());refs={}+for f in sexp.find(b,'footprint'):+ props={v[1]:v[2]for v in sexp.find(f,'property')};at=sexp.first(f,'at');refs[props['Reference']]={'at':[float(x)for x in at[1:]],'model':[m[1]for m in sexp.find(f,'model')]}+# Bounding boxes extracted from fitted generic KiCad STEP, not manufacturer qualification.+header_bbox={'J9':[-1.27,-6.35,-3,1.27,1.27,8.54],'J10':[-1.27,-3.81,-3,1.27,1.27,8.54]}+def project(ref,box):+ at=refs[ref]['at'];x,y=at[:2];a=math.radians(at[2]if len(at)>2 else 0);co,si=math.cos(a),math.sin(a)+ pts=[(x+co*u-si*v,y-si*u+co*-v)for u in [box[0],box[3]]for v in [box[1],box[4]]]+ return [min(t[0]for t in pts),min(t[1]for t in pts),max(t[0]for t in pts),max(t[1]for t in pts)]+headers={r:project(r,bb)for r,bb in header_bbox.items()}+candidates=[{'name':'Centered 50 mm sink','box':[102.46,46,152.46,96]}, {'name':'Offset 50 mm sink','box':[112,35,162,85]}]+for c in candidates:+ x0,y0,x1,y1=c['box'];c['probeKeepoutRadiusMm']=2;c['probeConflicts']=[r for r,d in refs.items()if r.startswith('TP')and x0-2<d['at'][0]<x1+2 and y0-2<d['at'][1]<y1+2];c['headerConflicts']=[r for r,bb in headers.items()if max(x0,bb[0])<min(x1,bb[2])and max(y0,bb[1])<min(y1,bb[3])];c['accepted']=False+report={'boardSha256':hashlib.sha256(board.read_bytes()).hexdigest(),'basis':'Nominal 50 x 50 x 10 mm sink and 40 x 40 x 20 mm fan; no assembly accepted','nominalStackMmAboveBoard':4.455+0.2+10+20,'notIncluded':['height tolerance','fan guard','mounting hardware','wire bends','installed airflow','case interface/spreading resistance'],'headerBoundsMm':headers,'candidates':candidates,'nextAction':'Offset candidate moves TP4 to (100.8,77.2), TP8 to (100.8,80), J9 to (154.6,98), rotation -90; native routing and full fitted-body acceptance remain required.'}+(p/'mechanical/cooling-envelope-review.json').write_text(json.dumps(report,indent=2)+'\n')+print(json.dumps(report,indent=2))

@@ -1,7 +1,8 @@ import json from pathlib import Path P=Path(__file__).resolve().parents[1];d=json.loads((P/'design/netlist.json').read_text())-s={'board':'Adom electronic load R0, 64 x 72 mm, 2 layers; engineering prototype', 'copperUm':35,'clearance':0.2,'edgeClearance':0.2,'fixedRefs':[c['ref'] for c in d['components'] if 'fixed'in c], 'wideNets':{n:[2.0,1.5,1.2] for n in ['DUT_POS','DUT_FUSED','LOAD_POS','SHUNT_P','GND']}, 'midNets':{'5V_AUX':[0.5,0.4],'V_GATE':[0.3,0.25]},'kelvin':{'U4.10':'RSH1.2','U4.9':'RSH1.3'}, 'chains':[{'refs':r,'direction':'down'} for r in [['R8','R9','R10'],['R18','R19'],['R22','R23'],['R27','R28'],['R35','R36','R37']]], 'loads':{n:{'amps':3,'maxRiseC':10} for n in ['DUT_POS','DUT_FUSED','LOAD_POS','SHUNT_P','GND']}, 'hot':{'Q1':{'watts':25,'tabNet':'LOAD_POS','maxRiseC':15,'note':'25 W target at assumed 40 C ambient and 55 C case trip. External heatsink unresolved; board-only solver is not cooling validation.'},'D1':{'watts':1.65,'tabNet':'LOAD_POS'},'RSH1':{'watts':0.18,'tabNet':'SHUNT_P'}},'hotMaxRiseC':35, 'pours':[{'net':'GND','polygon':[[98.3,30.3],[161.7,30.3],[161.7,101.7],[98.3,101.7]],'layers':['B.Cu'],'priority':0,'connection':'solid','name':'Power return and signal reference'}], 'notPoured':['BOOST_SW','SERVO_FB','SHUNT_P_SENSE','SHUNT_N_SENSE','I_SET','DAC_OUT','SET_DIV'], 'fab':{'rules':'fab','target':'fab'},'sourcing':{'profile':'fab'},'molecule':{'pin':'medium','gridMm':2,'edgeMarginMm':2,'cornerPinsNet':'GND'},'requireEvidence':['calcs','simulation'], 'qualificationNote':'Limits are simultaneous. MOSFET25W plus diode/shunt losses are conservative separate layout screens, not one physical operating point. Heatsink contact, mounted airflow, USB impedance, contact current ratings and prototype tests remain unverified.'}+s={'board':'Adom electronic load R0, 64 x 72 mm, 2 layers; engineering prototype', 'copperUm':35,'clearance':0.2,'edgeClearance':0.2,'fixedRefs':[c['ref'] for c in d['components'] if 'fixed'in c], 'wideNets':{n:[2.0,1.5,1.2] for n in ['DUT_POS','DUT_FUSED','LOAD_POS','SHUNT_P','GND']}, 'midNets':{'5V_AUX':[0.5,0.4],'V_GATE':[0.3,0.25]},'kelvin':{'U4.10':'RSH1.2','U4.9':'RSH1.3'}, 'chains':[{'refs':r,'direction':'down'} for r in [['R8','R9','R10'],['R18','R19'],['R22','R23'],['R27','R28'],['R35','R36','R37']]], 'loads':{n:{'amps':3,'maxRiseC':10} for n in ['DUT_POS','DUT_FUSED','LOAD_POS','SHUNT_P','GND']}, 'hot':{'Q1':{'watts':5,'tabNet':'LOAD_POS','maxRiseC':15,'note':'5 W compact prototype target at assumed 40 C ambient and 55 C case trip. External heatsink unresolved; board-only solver is not cooling validation.'},'D1':{'watts':1.65,'tabNet':'LOAD_POS'},'RSH1':{'watts':0.18,'tabNet':'SHUNT_P'}},'hotMaxRiseC':35, 'pours':[{'net':'GND','polygon':[[98.3,30.3],[161.7,30.3],[161.7,101.7],[98.3,101.7]],'layers':['B.Cu'],'priority':0,'connection':'solid','name':'Power return and signal reference'}], 'notPoured':['BOOST_SW','SERVO_FB','SHUNT_P_SENSE','SHUNT_N_SENSE','I_SET','DAC_OUT','SET_DIV'], 'fab':{'rules':'fab','target':'fab'},'sourcing':{'profile':'fab'},'molecule':{'pin':'medium','gridMm':2,'edgeMarginMm':2,'cornerPinsNet':'GND'},'requireEvidence':['calcs','simulation'], 'qualificationNote':'Limits are simultaneous. MOSFET5W plus diode/shunt losses are conservative separate layout screens, not one physical operating point. Heatsink contact, mounted airflow, USB impedance, contact current ratings and prototype tests remain unverified.'} s['planes']={'GND':'B.Cu'}+s['netClearance']={'USB_VBUS':0.27} s['loads']['5V_AUX']={'amps':0.3,'maxRiseC':10} (P/'design/spec.json').write_text(json.dumps(s,indent=2))

@@ -1,5 +1,5 @@ {-  "rawTakeCount": 42,+  "rawTakeCount": 43,   "reviewedExcerptCount": 16,   "countingRule": "Unique raw window recording filenames in this project; excludes derivative action/speed exports and reference projects. Raw count includes rejected takes.",   "takes": [@@ -254,6 +254,12 @@       "durationSeconds": 44.333333,       "topic": "AIFlow routing/thermal revisit checkpoint",       "review": "Automatic checkpoint recording; static review time, not original copper construction; editorial review pending."+    },+    {+      "file": "videos/raw/window-5969372-20261009-134507.mp4",+      "durationSeconds": 98.066667,+      "topic": "Pup manufacturer heatsink research after direct HTTP 403",+      "review": "Full decode and contact sheet reviewed. Real navigation to product and technical/CAD table; substantial static time to remove. CAD download points to sign-in; not a successful CAD download."     }   ] }