Adom Custom Electronic Load

@@ -101,3 +101,5 @@ TP8,TEMP_SENSE,no part,,none,,,,,bare copper; no purchased part TP9,HW_OK,no part,,none,,,,,bare copper; no purchased part
 TP10,LATCH_Q,no part,,none,,,,,bare copper; no purchased part
 TP11,GND,no part,,none,,,,,bare copper; no purchased part
+TP12,FAN_TACH,no part,,none,,,,,bare copper; no purchased part
+TP13,SHUNT_N_SENSE,no part,,none,,,,,bare copper; no purchased part

@@ -0,0 +1,26 @@+{+  "extracted_by": "service-step2glb 0.2.0",+  "extracted_at": "2026-10-08T13:48:39Z",+  "bbox_mm": {+    "x": [+      -4.5,+      4.5+    ],+    "y": [+      -4.5,+      4.5+    ],+    "z": [+      -0.0,+      1.5+    ]+  },+  "floor_z_mm": -0.0,+  "top_z_mm": 1.5,+  "longest_axis": "x",+  "pin1": {+    "source": "unknown"+  },+  "duration_ms": 1073,+  "warnings": []+}\ No newline at end of file

@@ -0,0 +1,17 @@+# Library review checkpoint — 2026-10-08++`tools/audit_library.py` checks the actual 104-reference candidate against the connectivity source: each numbered pad has the intended net, MPN fields match, and required model files exist with recorded hashes. Bare test pads require no fictitious component body. This structural audit passes; it does not certify manufacturer geometry or production readiness.++The native schematic export matches all 52 intended nets. Native ERC and placement DRC have zero findings; 220 connections remain unrouted. Native 2D and linked 3D views show the two added probe pads. No cooling assembly is present.++## MCU package screening++ST DS13560 Rev 6, Figure 3 page 36 and Table 82 page 127 identify the selected GP LQFP32 variant. Its package has a 7 mm body, 9 mm lead span, 0.8 mm pitch and 1.6 mm maximum height. The retained KiCad generic model measures 9 × 9 × 1.5 mm and is seated at z≈0. Its model tool reports pin-one recognition unknown, so that automated result does not verify orientation. The board footprint has 32 pads at 0.8 mm pitch. Its 1.5 × 0.5 mm pads differ from ST's example land pattern; retain this distinction for assembly review rather than claiming exact manufacturer CAD.++Source: [ST STM32G0B1 datasheet](https://www.st.com/resource/en/datasheet/stm32g0b1kc.pdf). Exact-MPN wiki search found no component page; the suggested R-package part is not an equivalent package and was not substituted.++## Pin-function checks against downloaded primary documents++The selected DGS DAC's power, output, I2C select, clock/data, address and reference assignments agree with Table 6-1 in `dacx0501.pdf`; NC pins remain unconnected. OPA189 DBV input/output and supply assignments agree with Table 6-1. INA226's supply, sense, bus, address and I2C pins agree with Table 4-1. SN74LVC1G175's latch input, clock, clear, output and supply assignments agree with its pin-functions table. These checks confirm selected assignments, not complete circuit behavior.++Still required: the remaining exact-package pin/function reviews, manufacturer geometry and polarity comparisons, model source/licensing coverage, marked variants where required, connector/lead mechanical qualification, full assembly BOM inventory, cooling/mount geometry and final native assembled-clearance review. AIFlow remains at libraries; its models and later gates have not been declared complete.