project
Adom Custom Electronic Load
Public Made by Adomby adom
Two-layer digitally controlled electronic-load prototype. Compact R11 is under active electrical, cooling and probe-access review; not a manufacturing release.
← Commit history
Record failed finer-mesh diagnostic without thermal qualification claims
3 files changed
+15−2
design/fields-two-layer-fine.logadded+6@@ -0,0 +1,6 @@+5V_AUX: 0.3 A, 2 layer(s), 2846 iterations, residual 9.8e-8+DUT_FUSED: 3 A, 1 layer(s), 347 iterations, residual 8.4e-8+DUT_POS: 3 A, 2 layer(s), 1829 iterations, residual 9.3e-8+GND: 3 A, 2 layer(s), 6000 iterations, residual 3.8e0+LOAD_POS: 3 A, 2 layer(s), 1581 iterations, residual 9.8e-8+SHUNT_P: 3 A, 2 layer(s), 675 iterations, residual 7.6e-8
design/fields-two-layer-provenance.json+8−1@@ -22,5 +22,12 @@ }, "tests": 18, "productionBuild": "passed",- "guardAcceptedSummaryExists": false+ "guardAcceptedSummaryExists": false,+ "fineMesh": {+ "pitchMm": 0.1,+ "groundIterations": 6000,+ "groundResidualApprox": 3.8,+ "status": "stopped after DC nonconvergence; thermal not completed",+ "acceptedSummary": false+ } }
docs/fields-review.md+1−1@@ -12,4 +12,4 @@ Five loaded nets converged, but GND exhausted 6000 iterations with residual 316. The revised source checks every DC residual before publishing a summary. Repeating the actual board at 0.2 mm now returns an explicit nonconvergence error and emits no fields.json. [Guard log](../design/fields-two-layer-guard-check.log). -A 0.1 mm mesh is being examined to distinguish raster/solver limitations. Neither a converged field plot nor native DRC would establish MOSFET SOA, junction temperature, the external heatsink/fan assembly, or hardware shutdown performance. The board is not released for fabrication.+At 0.1 mm, GND again exhausted 6000 iterations (residual approximately 3.8). The task-owned run was stopped after this electrical failure, before completing thermal analysis. No accepted summary exists at either mesh; this establishes an unresolved solver/raster limitation, not a physical open in the DRC-clean board. [Fine-mesh log](../design/fields-two-layer-fine.log). Neither a converged field plot nor native DRC would establish MOSFET SOA, junction temperature, the external heatsink/fan assembly, or hardware shutdown performance. The board is not released for fabrication.