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AI Flow

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Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board.

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thermal-vias --ack still lands; heatsink vias ignore silkscreen; stitchVias size defaults

John Lauer · ·closed by John Lauer

Version: adom-aiflow 0.2.17, KiCad 10.0.5, KiCad Bridge 1.0.58 (Windows desktop).

Three things from one live KiCad run (a 60 x 84 mm 2-layer sensor board, readout landed live through the bridge):

  1. thermal-vias land --ack REF --why still lands the plan. The ack only clears the shortfall check (main.rs ThermalVias land: it runs land vias --plan <plan> whenever the plan has nets). Expected: --ack U3 leaves U3's planned vias out of the landing. Workaround used: empty the plan file, then land --ack.
  2. The heatsink via planner ignores silkscreen. For U3 (SOT-23-5, 0.085 W) it placed six 0.6 mm vias under the part's own reference and value labels. They pass KiCad's DRC (the vias are tented), but the labels become unreadable, and silkscreen-audit --record then fails for missing via boxes. Expected: existing silk text and graphics are obstacles for planned vias, as they are for the silkscreen placer.
  3. stitchVias default to 0.8 / 0.4 mm. Each entry can carry size and drill, but nothing says so in the hint or docs/spec-example.json. The default refused a stitch via 0.15 mm from an LED pad that the board's real 0.4 mm via clears. Suggest: default to the spec's or board's via size, and name the keys in the refusal hint.

Also seen: aiflow's landing check defaulted to 0.2 mm via-to-via copper clearance, while the board's 3rd party fab pack allows 0.1 mm, and refused vias KiCad's DRC passes until clearance was set in the spec. Reading the clearance from the project's .kicad_dru would avoid that.

1 Reply

John Lauer ·

Fixed in adom-aiflow 0.2.19, all four.

  1. --ack no longer lands the acknowledged parts' vias. Plan entries now carry their ref, and thermal-vias land filters acknowledged parts out (older plans are matched by their why text). It lands plan-thermal-vias-landing.json and records leftOutAcked.
  2. Via planners avoid silkscreen. Visible silk text (with justification and ${REFERENCE}/${VALUE}) and silk graphics on both sides are obstacles, using the same text-extent estimate as the silkscreen audit. Both the heatsink planner and the small-pin ring in pour keep silkClearance (default 0.1 mm), and say how many spots the silk took when a part ends up short.
  3. stitchVias defaults: an entry with no size/drill takes the spec's viaSignal/drillSignal, else the board's most common via, else 0.6/0.3 (was 0.8/0.4). The messages and docs/spec-example.json name the size and drill keys. (The 0.15 mm-from-an-LED via was dropped by pour with a printed note, not refused by a hint.)
  4. Clearance from .kicad_dru: via-to-via clearance and hole-to-hole come from the spec if set, else from the project's .kicad_dru (rules with no condition or a via-only condition, last one wins, as in KiCad), else 0.2 mm. This applies to land vias, pour and thermal-vias plan. It ignores net-class and area rules.

Upgrade: adom-wiki pkg install adom/adom-aiflow, then adom-aiflow --version says 0.2.19.

John Lauer closed this ·

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