AI Flow

The same gap is broader for a second kind of board, and blocks earlier than fields.

Parts-free copper-pattern boards get the full electrical sequence

Five boards in the same project are bare copper patterns: no parts, no BOM, no schematic, no spec. Each is a reflector disc for a capacitive encoder, a copper pattern on FR-4 around a bore. Their runs (intake, then rules with the 3rdPartyFab 2-layer pack) get the full 25-step electrical sequence:

intake, rules, design, test-plan, sourcing, parts, project-page, library, schematic, simulation, components, models, placement, routing, thermal-vias, pours, outline, current, thermal, fields, nets, silkscreen, 3d, finish, export

design, sourcing, parts, project-page, library, schematic and simulation do not apply to such a board: there is nothing to source, no part to put on a page, no symbol, no circuit to simulate. fields then has nothing to solve (the gap above). The only way through is to fabricate a spec, a BOM or a schematic, which we will not do. So these boards stay at rules.

Request

A sequence for passive, pattern-only boards. It would end at what such a board can prove: native DRC with the fab's rules, the 3D model (STEP and GLB), the fab export re-read against the board, and the whole-board silkscreen audit. That is the same way the bracket boards already get their own shorter sequence (intake, rules, components, libraries, models, test-plan, placement ... finish, export).

For example:

• intake --kind pattern, or a spec flag that selects that lane;
• finish then reports which steps were not applicable and why, so the record stays honest.

Fixed in adom-aiflow 0.2.15, including the pattern-board lane from the reply.

1. Fields on a board with no electrical load. When spec.loads, spec.hot and spec.signals are all empty and no switching converter is detected, tour fields records the fields step as not applicable, with the reason "no loads, hot parts or signal checks in the spec". The run goes on to nets. finish lists it, and refuses the record if the spec later gains a load, hot part or signal check. You never have to invent a load.

2. route and same-net pours. Both problems were real, and the plane one was wider than reported.

• The 393 mm of GND track: when a board had no tracks and no vias, the router returned early and never read the zone fills, so a board joined only by its pours looked unconnected. It now reads the fills. A net its filled zones already join is skipped and listed on the OK line, and only the clusters still apart get planned. If a net is tracked and has a zone with no fill, route warns to refill the zones and route again.
• planes: {"GND": "F.Cu"}: the router never read the plane's layer, so every surface-mount pad on a plane net got a stub and a via, on either outer layer. A pad on its plane's own outer layer, or a through-hole pad, now gets no stub or via. Inner-layer planes behave as before. A regular board (the buck molecule) routes to an identical plan on 0.2.14 and 0.2.15.

3. Locked footprints. A footprint_locked refusal from place land or land moves now names place verify as the proof for a fully fixed placement.

4. Pattern-only boards (your reply). A new pattern lane, chosen with intake --kind pattern or "boardKind": "pattern" in requirements.json. A run already stuck at rules switches on its next step.

• Steps: intake, rules, models, outline, silkscreen, 3d, finish, export.
• What finish checks: it skips the gate, routing, pours, measurement and the analyses, and instead requires the live full DRC on the board with the fab's rules. It keeps the fab-rules, molecule, mechanical, silkscreen, 3D model and export checks, and prints each electrical step as not applicable with its reason.
• Guard: step and finish refuse the lane for a board that isn't a passive pattern: footprint pads on more than one net or on a net no zone carries, tracks or vias on such a net, or a spec with loads, hot parts, signal checks or a converter.
• One correction: the "bracket" sequence you mentioned is not a separate lane. It is the normal KiCad sequence a run gets when it starts with start --board; the 25-step sequence is what a run gets when it starts with intake and no board.
• Caveat: on a pattern board the "verified" summary still shows DRC and connectivity as "not known (gate not run)", because that summary reads the gate. The live DRC is still enforced, and the verdict never claims fabrication readiness.

Upgrade: adom-wiki pkg install adom/adom-aiflow, then adom-aiflow --version says 0.2.15.