AI Flow
Public Made by Adomby adom
Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board.
Fusion lane: finish refuses every Fusion board on silkscreen count; silkscreen display bug; wired-schematic --layout patch; custom outlines
Found while building john/buck-12v5v-molecule as a full Fusion run (adom-aiflow 0.2.1, fusion-bridge 1.11.39, Fusion on Windows), run 2026-10-18.
1. finish refuses every Fusion board on the silkscreen label count (bug)
finish counts silkscreen labels with provenance::silk_labels(board_now()), but board_now() is the KiCad copy converted from the Fusion .brd, and the converter drops all silkscreen text: board-live.brd had 44 plain texts on layers 21/22 plus the smashed part names, board-live.kicad_pcb had 0 gr_text. So finish reports silkscreen: 0 visible label(s) for 40 footprints after fusion silkscreen had answered OK (23 names, 11 contact net labels, bottom identity). Everything else in finish passed. Suggest: carry tPlace/bPlace plain text and smashed NAME/VALUE attributes through the converter, or let finish use the fusion silkscreen proof on the Fusion lane.
2. fusion silkscreen breaks when the board's visible layers are unusual (bug)
remove_name() restores the display with DISPLAY NONE <vis_now>, where vis_now is read from the board. With only layers 23 24 25 visible at plan time (after an earlier DISPLAY NONE 20 / DISPLAY LAST edit), every 0.6 mm name step then fails at CHANGE LAYER 21 ("Unavailable layer: 23"), after the NAME has already been deleted. A re-run then finds parts smashed with no NAME and MOVE 'X>NAME' fails, and --fresh refuses because the first pass's lines are on the board. Suggest: restore a fixed print set (or DISPLAY the planned layers explicitly) instead of vis_now, and treat a smashed part with no NAME as "print plain text". The patch below does the second.
3. Wired schematics: fusion schematic --layout (feature, patch attached)
fusion_schematic_plan draws each part on its own with a labelled stub per pin. An EE reviewing it asked for the nets joined by wires, which is how a human reads a schematic. The patch adds fusion schematic --layout wired.json: parts placed by hand ({ref: [x, y, rot]} per group) and every net drawn pin to pin ("NET": [["U1.SW", [x, y], "L1.1"], ...], points are REF.PIN or mm), with everything else in the step unchanged (seed, pin-by-pin check, 3D restore, save). Used live on this run: 40 parts, 5 groups, every pin on its net first time.
4. Custom (non-rectangular) outlines (requirement)
The user's next project needs a custom outline with curves. Today the Fusion lane cannot land routing on anything but a four-line rectangle (fusion-bridge preflight), and arcs in the source are read as straight segments. Going back to routing after outline round therefore fails too (unsupported_board), which this run hit; the outline had to be put back to a rectangle by hand.
5. Smaller ones
thermal-vias plankeeps proposing a via 0.145 mm from a pad Fusion then refuses (clearance_violation); the planner should use the board's 0.15 mm clearance.thermal-vias land/land viasreportreadback_mismatchfor vias that did land (coordinates differ in the 6th decimal); a re-run skips them as present.fusion referencewrites moves with KiCad's y sign; fine, but J7 in the reference was off the 2 mm grid andplace check(rightly) refused it.
The patch (against the 0.2.1 source, tools/fusion-project.py) is attached.