rules: install ignores --layers; gate cannot match a JLC 6L pack; plan JSON shape undocumented

Closed general

John Lauer · 7d ago ·closed by John Lauer

Found on a 6-layer JLC board (adom-aiflow 0.1.91).

rules install --profile jlcpcb --layers 6 --board X --force writes the 2-layer pack (installed the jlcpcb-2L rules): it ignores --layers, and it silently replaced the 6L pack rules use had installed.
The gate's rules check with spec fab.rules: "jlcpcb-6L" looks for a pack file jlcpcb-6l-6L.kicad_dru, which does not exist. With fab.rules: "jlcpcb" it compares the board's rules against the shipped 2-layer profile, whatever the layer count, so a correct 6L board fails as "another rules file". What works: fab.rules: "fab" (the project's own .kicad_dru), with the 6L pack from rules use --profile jlcpcb --layers 6 in that file. The hint never says so; it points at rules install, which makes it worse (item 1).
rules use before the board exists (an intake run) does not write fab.rules into the spec, because there is no spec yet. start --spec then carries whatever the spec says, and nothing ties it to run.json fabRules ({profile: jlcpcb, layers: 6, file: jlcpcb-6L.kicad_dru}). The gate could read fabRules when the spec disagrees.
The route plan shape for gate --plan / land route --plan is undocumented. {"entries": [...]} fails with "plan needs nets"; the code wants {"nets": [...]} or a bare array (aiflow-copper apply). A via with copper on only one layer (pad on F.Cu, track on In2) needs its own entry [[x,y],{x,y,layer}]. Worth a short schema in the high-speed section of SKILL.md.

John Lauer · 5d ago

Fixed in adom-aiflow 0.1.94.

rules install takes the layer count from --layers, else a -6L style suffix, else the board's copper layers, else run.json fabRules, else 2. A count with no shipped pack is refused with a pointer to rules use --profile jlcpcb --layers <n>; replacing a different pack needs --force, keeps a .kicad_dru.bak, and says what it replaced.
The gate reads jlcpcb-6L as profile jlcpcb with 6 layers, and a plain jlcpcb is judged by the board's copper layer count; hints name the right command for the layer count.
Gate, finish and rules check fall back to run.json fabRules when the spec has no fab.rules, and warn when they disagree (the spec wins). The 542a3c34 current-board recording is kept.
The plan shape is in docs/plan-schema.md and the High-speed section of SKILL.md; plan needs nets errors spell out the accepted shapes, and land route now lands a bare-array plan instead of silently landing nothing.

Upgrade: adom-wiki pkg install adom/adom-aiflow, then adom-aiflow --version says 0.1.94.