etch: reversed top-face normal rejects KiCad TSSOP-16/SOIC-8; TSSOP mark axis crosses pin rows

Overview Files Skills Discover Packages Releases Dependencies Issues6 Breadcrumbs Pull Requests Activity

Closed general

John Lauer · 7d ago ·closed by John Lauer

Found while etching the ICs of an OCP NIC 3.0 to OCuLink riser (adom-aiflow 0.1.91, KiCad 10.0.5 stock models).

1. mark_plan: no flat upward face near the top of the part on KiCad's own TSSOP-16 and SOIC-8 models

Package_SO.3dshapes/TSSOP-16_4.4x5mm_P0.65mm.step and SOIC-8_3.9x4.9mm_P1.27mm.step: the service's step_meta reports the top face (bbox z 1.1..1.1, x -2.075..2.075, y -2.375..2.375) with normal: [0, 0, -1]. The face is stored reversed in the STEP. _planar_up() accepts only n[2] > 0.99, so the part has no top face and the etch exits. TSSOP-14 from the same library passes. A local workaround that makes it work: abs(n[2]) > tol. A flat face at the top of the body's bbox cannot face down, so the bbox position decides, not the sign of the normal. --face top does not help (same check).

2. TSSOP: the mark runs across the pin rows, pin 1 upper-left

On TSSOP-14/16 (4.4 x 5.0 body, pin rows along Y) the planner's top band is 4.15 x 3.78 mm. The pin-1 dimple trims the band's long side, so it picks X and marks across the pin rows with pin 1 upper-left (it warns "pads are numbered clockwise"). The skill's rule says ICs are marked parallel to the pin rows. --along y then makes the gate WARN ("across the short side"). The gate and the rule disagree. Suggest: for packages with two pin rows, the axis follows the pin rows (body length), and the dimple trims the band without changing the axis.

The check images are in the riser project; I can attach them.

1 Reply

John Lauer · 5d ago

Fixed in adom-aiflow 0.1.94. (1) A flat face counts as horizontal by |n_z|, and one stored pointing down counts as the top only when it sits at the top of the bbox, so KiCad's stock TSSOP-16 and SOIC-8 now plan (a hint says the face was stored reversed). (2) The planner reads two pin rows from the footprint pads (exposed pads and thermal vias ignored; QFN and SOT-223 are not two-row): the mark runs along the rows and the pin-1 dimple only shortens the band. TSSOP-16 plans along Y on the 3.78 mm band, pin 1 lower left; TSSOP-14 and SOIC-8 the same. --along along the rows no longer warns, and text across an IC's pin rows now FAILs the gate. Checked end to end on the real KiCad models through the STEP service: TSSOP-16 74HC595PW, SOIC-8 NE555DR and R_0603 all PASS.

Also in this release: the shared service's /laser-etch now returns Adom.Chip and Adom.LaserEtch as two top-level products, which broke every etch in graft() on 0.1.93. 0.1.94 accepts both the old and the new shape (test_step_graft.py). Upgrade: adom-wiki pkg install adom/adom-aiflow, then adom-aiflow --version says 0.1.94.