AI Flow
Public Made by Adomby adom
Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board.
Detect stale planned pour regions before thermal-via counts
During the custom electronic-load run, a diode rotation and accepted native zone relocation left spec.pours describing the old polygons. AIFlow 0.1.76 thermal-vias plan reported D1 existing 0 / planned 0 without identifying the mismatch. Reconciliation against the exact accepted board (SHA 653e54e711552eb2f16b6d01cd144fd82645a52c30ff11e39699b760402af51a) changed this to existing 1 / planned 9. No board geometry changed during reconciliation.
The via-locality checks from issue #38 are appropriate; this is a separate input freshness problem. Recommend comparing declared planned zone geometry to existing board zones before planning/counting, emitting a focused mismatch hint with net/layer/name and recording both hashes. Distinguish intentionally unlanded pours from stale accepted pours. Never silently expand copper or acknowledge the via gate to clear the warning. Native refill/DRC and actual thermal qualification remain required.
Evidence on adom/adom-custom-electronic-load: design/pour-spec-reconciliation.json, tools/reconcile_pour_spec.py, board 17 native DRC, and design/spec.json. The nine-via candidate is under separate native/electrical review. This report is a requested shared feature, not a released implementation.