Checks to add from an outside engineer's full trial: symbol polarity, pin types, readable schematics, exact parts, courtyards, body overlap, ground fill really exported, honest readiness

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John Lauer · 11d ago ·closed by John Lauer

An outside analog engineer ran a full trial (October 2026): a buffered RC low-pass filter, then a from-scratch diode voltage-controlled attenuator through schematic, PCB, simulation and manufacturing outputs (3 h 14 min, Codex). The package was impressive: native schematic and PCB agreed electrically (26 parts, 16 nets), recovery from tool failures was good, and limits were reported honestly. But several defects reached the "complete" package, and the AI's own checks did not catch them. Each one below is something the flow can make the AI check before it calls a stage done.

Schematic correctness and readability (aiflow-circuit-design)

Custom symbol graphics must match pin declarations. A custom diode declared pin 1 = K on the left, but drew the cathode bar on the right. Nets, pads and SPICE were all correct, so the drawing contradicted the circuit. Add a check: for every custom symbol, the drawn polarity marks (diode bar, transistor arrow, op-amp +/-) agree with the declared pin names and numbers.
Pin electrical types must be real. A custom TL072 declared all four amplifier inputs passive, which quietly weakens ERC (a zero-warning ERC then proves less). Add a check: amplifier inputs are input, outputs are output, power pins are power_in; no passive on active-device pins unless the datasheet says so. Prefer library symbols (one triangle per op-amp section, a conventional transistor symbol) over custom rectangles and circles.
Draw the signal path; don't label every pin. The sheet had 63 local labels and zero wires, which hid the follower loop, the servo loop and the diode bridge. Add a rule: local connections inside a functional block are drawn wires, and labels are only for long or cross-sheet nets. Feedback loops must be visibly traceable. Keep text off pins and parts inside the drawing border.

Exact parts and datasheet reading (aiflow-sourcing)

Prove the exact manufactured part exists. A KEMET 0805 capacitor part number was decoded from the part-number grammar, but the family selection table did not list that exact combination. Add a step: cite a manufacturer or distributor page for the exact MPN (value, tolerance, dielectric, voltage, package), not only the family datasheet.
Typical is not maximum. An MCP6001 input bias current of 19 pA at +85 °C was called a maximum, but the datasheet lists it as typical. Add a check: every datasheet number quoted in a calculation is tagged typ, min or max, and worst-case math uses guaranteed limits.
Don't freeze component values unnecessarily. When a part was unavailable, the AI insisted on keeping 100 nF ±1% instead of re-deriving the RC pair (for example 15.8 kΩ / 10 nF). Allow equivalent value pairs that meet the spec.

Mechanical and physical checks (aiflow-schematic-to-board)

Every footprint needs a courtyard. None of the 26 footprints had one, so KiCad's courtyard overlap check had nothing to compare. Add a courtyard step: fail any footprint without F.CrtYd/B.CrtYd, then run courtyard overlap as an error, not ignore.
Check body overlap too. C6 at (105, 75.5) and C7 at (105, 79.5) each draw a 5 mm body, centres 4 mm apart, so the bodies overlap by 1 mm. This passed because there were no courtyards. Add a check: fabrication-layer body outlines (or 3D model bounding boxes) don't intersect.
Footprint bodies must match the real part. A Phoenix 1715721 terminal footprint drew a 7 mm body, but the datasheet says 9.8 mm. Check the body depth against the datasheet for connectors and large parts.

Ground fill and pours really in the delivered board

The board that is checked must be the board that ships. The report described a refilled ground zone with one isolated-fill DRC warning, but the saved board had a B.Cu zone with zero filled_polygon objects, and the bottom-copper Gerber had zero G36 regions. Add a final gate: refill zones, save, then assert that the saved file contains filled polygons for every zone and that the exported copper Gerbers contain the pour regions. Fail the stage if not.

Assembly output (aiflow-silkscreen)

All reference designators were on F.Fab, none on silkscreen. Put readable refs and polarity marks on the silkscreen, with connector/function labels.

Honest stage messages

Don't overclaim readiness. A parity check's message told the AI the board could go to fabrication without human review. Electrical parity plus DRC (without courtyards) is not manufacturing readiness. Stage summaries should state exactly what was verified (connectivity, ERC, DRC, courtyards yes/no, fill exported yes/no) and never "ready to fabricate" unless every one of those passed.

Simulation scope (aiflow-simulate)

The design met ≥10 dB attenuation at 100 mVpp, but only 0.83 dB at 12 Vpp; the report disclosed this, which was good. When the spec includes a full-scale input, simulate at full scale too and flag a topology that only works small-signal (the reference design scaled the signal down before the diode ladder and restored the gain afterwards).

The trial also noted heavy token use and long runtime. Clear per-stage checkpoints would help users see where the time goes.

Community PRs that add any of these checks are very welcome.

3 Replies

John Lauer · 11d ago

14. Stair-step traces: route in clean 45° segments (aiflow-schematic-to-board, routing)

On this board, several diagonal runs are drawn as long staircases of tiny alternating horizontal and vertical segments instead of one straight 45° segment. The worst are the diode-bridge feeds and the control path. They're electrically fine, but they look machine-made, add needless vertices and acid traps, and are hard to edit. John had not seen Codex route like this before. It is likely the AI emitting a grid-stepped path point by point.

Check to add after routing, before the gate:

For every track chain on a net, collapse collinear consecutive segments into one.
Flag a staircase: three or more consecutive segments, each shorter than about 2× the track width, alternating between 0° and 90°. Replace the run with a single 45° segment (plus at most one orthogonal leg) between its end points, and re-run DRC on the changed copper.
Report the vertex count per net before and after. A clean two-layer board like this should need only a few vertices per connection.

Guidance for the AI (Claude or Codex), in the routing skill: draw each connection as straight runs joined by 45° corners. When a path comes out of a grid search, simplify it before writing it to the board (merge collinear points, then replace diagonal staircases with true 45° segments), and look at the rendered copper once before calling routing done.

This is the kind of check outside contributors could add. A PR with a small staircase detector and simplifier would help every board the flow routes.

John Lauer · 8d ago

Board32 export evidence for the existing completeness-check request.

Environment: Windows native KiCad 10.0.5, KiCad Bridge 1.0.55, Adom Bridge 2.1.174; AIFlow installed 0.1.90, this run explicitly uses reviewed source d985e4ac858ea5a6ca257ee423e1b4288e9787fe. Shared pinned runtimes were preserved.

A full native STEP export with --subst-models --include-tracks --include-pads --include-zones --include-soldermask --include-silkscreen exits 0 and creates the file, but prints six instances of Wire self-interference check failed at z=1.585. Bounds map near U3, Q2, Q3 and Q4. The original report and exact bounds are attached. The saved board is ea37ce6db20bae331bf41b6638fe9149a17c484e01bc2a0d7fd34917203b7fc3 and native project DRC is zero violations / zero opens.

Controlled read-only exports: --min-distance 0.001mm retains all six warnings; excluding soldermask also retains six; excluding silkscreen gives zero warnings. These omitted-layer exports are diagnostics only and are not adopted as a workaround. No PCB or native editor geometry changed.

All 1,191 imported solid bodies in the original STEP are BREP-valid. That cannot prove completeness of the exported silkscreen faces. KiCad 10.0.5's MakeShapes code tries a polygon fallback after the warning and can also skip an outline/hole at debug severity; the warning alone does not establish whether fallback succeeded. Source: https://github.com/KiCad/kicad-source-mirror/blob/10.0.5/pcbnew/exporters/step/step_pcb_model.cpp

Requested integration check: preserve and classify native export diagnostics separately from process exit and model/material checks, and require an explicit completeness review before final twin delivery when geometry warnings remain. Do not hide the warning by omitting a required layer or changing circuit geometry to chase an exporter artifact. This is an owner handoff with reproducible evidence, not a source fix, release or deployed feature. Current project thermal and export acceptance remain open.

native-export.json

warning-locations.json

no-silk-diagnostic.json

John Lauer · 1d ago

Most of this trial is now enforced in adom-aiflow 0.2.3:

Custom symbols whose drawn polarity contradicts the pin names are errors. passive on op-amp or comparator inputs, outputs or power pins is an error (a warning on other ICs). Readability problems (labels without wires, text over pins) are warnings. finish requires the pass.
sourcing check wants an exact-MPN page per row (an error under requireExactMpnEvidence). evidence add warns on untagged datasheet numbers, worst-case maths on typical values, and a missing full-scale simulation case.
Missing courtyards, courtyard overlaps and body overlaps are errors in place check, gate and finish, whatever the project sets. On a real board this flagged 3 footprints without courtyards. spec.bodies checks a drawn body against the datasheet size.
export and finish require filled polygons for every zone in the saved board and region (G36) data in each poured layer's Gerber.
route simplifies staircases into 45-degree runs and reports vertices per net, and gate warns about any left.
The new step-export keeps KiCad's geometry warnings apart from the exit status and needs an --ack --why before the board GLB and delivery.
gate, export, finish and deliver list what was verified (yes, no or not known) and never say ready to fabricate.
Silkscreen reference and polarity marks are checked at finish, with guidance in the companion skills. Upgrade and run the trial again; any check that misfires is welcome here. Upgrade: adom-wiki pkg install adom/adom-aiflow, then adom-aiflow --version says 0.2.3.