Router proposes vias overlapping USB NPTH holes; native manufacturing gate rejects them

Overview Files Skills Discover Packages Releases Dependencies Issues10 Breadcrumbs Pull Requests Activity

Closed bug report

John Lauer · 1mo ago ·closed by John Lauer

AIFlow 0.1.65 proposes routes whose vias violate native drill/NPTH clearance on the two-layer custom electronic load. The independent native gate correctly rejects them; no proposed bulk routes were landed.

Reproduction: adopt the native saved placement and bottom GND plane, then route --passes 5 and gate. The planner reports four unclosed sense connections. Native KiCad 10.0.5 gate finds 32 new manufacturing errors: 28 hole-clearance and 4 hole-to-hole findings (some report pairs may repeat). Native placement baseline is zero violations. Bridge 1.0.55 on Windows.

Concrete example: a proposed GND via at (156.3,39.8) overlaps the J8 non-plated hole at (156.3,40.11). The analogous lower hole has a proposed via at (156.3,46.2), hole centre (156.3,45.89). Native reported actual hole clearance zero. Expected: drill shapes and required drill/copper clearances participate in all plane-stub, via-search and via-in-pad candidate checks, including holes without an electrical net. Do not relax native rules to clear this failure.

Evidence attached is a reduced native gate report, with no private fabrication rulepack. Full local checkpoint: adom-custom-electronic-load/checkpoints/router-attempt-04. Current design page: https://wiki.adom.inc/adom/adom-custom-electronic-load

Workaround in progress: retain the native gate; manually preflight specific signal branches and repair/reject offending proposals. No source fix, release or deployed availability is claimed. Please add a focused NPTH-neighbour regression and verify all candidate-via entry paths, not just ordinary net routing.

router-hole-spacing.json

2 Replies

John Lauer · 1mo ago

Status at 0.1.94: the unnumbered-pad obstacle change is in source. aiflow-board keeps unnumbered pads, the router stamps them as no-net copper blocking vias on both layers, and a new regression (unnumbered_npth_mounting_hole_blocks_vias_and_tracks) passes for both *.Cu and F&B.Cu NPTH layer spellings. Remaining gap: an NPTH pad with no copper layer at all (only *.Mask) is still skipped by the board reader (if !copper { continue; } in aiflow-board/src/lib.rs), so the router and aiflow_pours::board_holes never see it. Fixing it in the reader touches every pad consumer, so it was left for a focused change. Keeping this open.

John Lauer · 27d ago

The remaining gap is closed in adom-aiflow 0.2.3. NPTH holes with no copper layer (mask only, for example USB-C shell pegs) are now kept in a separate Board.holes list. The router, board_holes (and with it the stitch and heat-via planners) and the pour masks keep clearance from them, and they never appear as pads to BOM, test plan, netlist or analyses. A regression test has a mask-only peg blocking a via. Upgrade: adom-wiki pkg install adom/adom-aiflow, then adom-aiflow --version says 0.2.3.

John Lauer closed this · 27d ago