AI Flow
Public Made by Adomby adom
Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board.
Add assigned-pin decoupling constraints and routed-path review before general rail routing
Versions/evidence: AI Flow 0.1.32 is validating and landing the F407 trial; original routes were generated by a task-local adapter of the older router source, with the already-reported no-net obstacle, minimum stub width and via-in-pad fixes. KiCad native DRC 10.0.2; desktop KiCad 10.0.5. This is a missing electrical-intent constraint observed in that trial, not a claim that 0.1.32 still has the closed router bugs.
Please support explicit local decoupling connections in the routing spec and acceptance report. On an STM32F407 LQFP144 molecule, 100 nF capacitors were physically about 1.5–2 mm from their assigned supply pins. DRC-clean supply trees nevertheless sent some through long rail detours: saved-plan endpoint measurements gave C6→U1.39 about17.36 mm (pad distance1.70 mm), C14→U1.131 about16.64 mm (pad distance1.88 mm). The measurement excludes incidental copper intersections, so these are graph-path observations, not impedance claims. Short direct supplemental connections can fit without moving parts or reducing .25/.15 routing rules.
Proposal: declare local pairs (capacitor supply pad, assigned MCU supply pin, capacitor ground pad, relevant MCU return pins), route/reserve those connections before general rail distribution, and preserve them during rip-up. Make layer-change and route-length budgets explicit per pair, with optional warning/error severity. Report assigned-pin path length separately from nearest same-net pin, and warn if the rail tree bypasses the intended local connection. Ground return checks should use actual refilled connectivity, not a straight-line distance across disconnected plane polygons.
DRC0/0 is necessary but does not validate this electrical intent. Do not invent a universal acceptable distance; use a board-specific budget and preserve the evidence for AI/human review.