AI Flow

adom-aiflow 0.2.78, gate on a 4-layer board: inner-layer-only zones are re-added as "planned pours" and DRC reports zones_intersect

gate_eval::with_planned_pours decides whether a planned zone is already landed with h.layers.iter().any(|&l| layers.contains(&aiflow_board::LAYER_NAMES[l])), and aiflow_board::LAYER_NAMES is ["F.Cu", "B.Cu"]. A zone that lives only on In1.Cu or In2.Cu (a solid GND plane on In1, a VBAT feed on In2) is therefore never seen as landed, so the gate copy gets a second copy of it and KiCad's DRC answers zones_intersect (same net, same priority) for every such zone.

Seen on a 4-layer power board: the saved board (101 zones, all filled, native kicad-cli DRC 0 errors / 0 unconnected) passes verify-pours --plan <plan pour wrote> --adopt, but gate --plan <empty plan> reports 6 new DRC errors {"zones_intersect": 6}, exactly the 6 zones whose layers are In1.Cu or In2.Cu only (gate.json newErrorList names each zone twice). Adopting the zones does not change it.

Suggested fix: compare layer names from the board's own layer table (or treat a planned zone as landed when an owned/ adopted zone with the same name, net and layer set exists), and extend the board model to inner copper layers. No Rust toolchain on this machine, so no PR from this run.