AI Flow
Public Made by Adomby adom
Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board.
Current gate falsely passes a narrow series bottleneck using the widest track
The 0.1.5 current gate can PASS a series path containing a severely undersized conductor. In crates/aiflow-analyze/src/lib.rs analyze_current, the first acceptance condition tests rise_wide rather than rise_narrow. This contradicts the stated narrowest-conductor check and is non-conservative even without any pour modeling.
Reproduction attached: a single POWER net has a 0.25 mm segment from (0,0) to (1,0), followed by a 40 mm segment from (1,0) to (2,0), at 20 A, 35 um copper, 10 C rise limit, no pours or vias. analyze_current returns pass=true, riseAtNarrowestC=12254, riseAtWidestC=2.9, and says the widest track carries the load. The enormous rise is the heuristic outside its meaningful range, but the false PASS is unambiguous.
Candidate fix: for the track-only acceptance branch, require the narrowest current-carrying series conductor to satisfy the rise budget; absent branch-current topology, fail conservatively on the minimum width. Add this fixture as a regression. Preserve separate explicit treatment of sense branches and independently proven pour bypasses.
Found during the fresh ESC measured run: https://wiki.adom.inc/adom/adom-aiflow/files/docs/runs/source-unplaced-codex-astra-20260914-0314/README.md . This finding does not claim that the ESC itself passes or fails current analysis yet.