export: BOM and CPL are not accepted by JLCPCB's assembly upload (AI Flow columns, KiCad rotations), yet export says verified

noah · ·closed by Colby Knox

Version: adom-aiflow 0.2.56 (local build 0.2.56+noah.1), KiCad lane, kicad-cli 10.0.6. Board: noah/rgbcct-canfd-led-driver (run fab target fab, the 3rd party fab profile).

What happened: the board was ordered at JLCPCB with the files export wrote (<run>/manufacturing/board-31-bom.csv and board-31-cpl.csv). JLCPCB's assembly upload refused the BOM: "File processing failed, please check your file and upload again."

  • The BOM export writes has AI Flow's own columns, Reference,Qty,Value,Footprint,Manufacturer,MPN,DNP, with the references space-separated (C2 C3 C4). JLCPCB's BOM needs Comment, Designator, Footprint, LCSC Part #, with the designators comma-separated in one cell.
  • The CPL is kicad-cli's raw position file (Ref,Val,Package,PosX,PosY,Rot,Side). JLCPCB needs Designator, Mid X, Mid Y, Layer, Rotation. Its rotation and origin must be those of LCSC's own (EasyEDA) footprint, and those differ from KiCad's on many parts. On this board: D1 BAT54CW 0 -> 180, D4 LED 0 -> 180, J1/J2 JST PH 0 -> 180 with the origin moved from pin 1, J7 FTSH-107 90 -> 0. Parts placed at KiCad's rotation come out wrong.
  • export still reports verified: ... yes and FAB-NOTES gives no hint that these files are not for any fab's uploader.

This is the second board to hit it: the LED strip run (adom/led-strip-500-rgbw) had to write its own jlcpcb_files.py.

Expected:

  1. export writes the order files for the fab the board is going to: for JLCPCB, BOM-jlcpcb.csv and CPL-jlcpcb.csv in their columns, with LCSC numbers from the sourcing record. It could keep the generic files beside them.
  2. The CPL rotation and position come from the LCSC footprint fitted onto the board's pads (easyeda2kicad gives the footprint), never KiCad's origin.
  3. The export check validates the order files against the fab's schema, and names any part without an LCSC number or short at JLCPCB.
  4. FAB-NOTES says which fab each file is for.

Workaround used: kicad/jlcpcb_files.py in the project. It reads the board, maps each MPN to LCSC with punctuation ignored, reads live stock (adom-jlcpcb part), fits each part's EasyEDA footprint (0/90/180/270, RMS pad residual under 0.12 mm) and writes both files plus a review sheet. Happy to send it as a PR if wanted.

1 Reply

Colby Knox marked this in progress ·
Colby Knox linked pull request #76, which closes this when it merges ·
Colby Knox closed this in pull request #76 ·
Colby Knox ·

Thanks Noah, this is fixed and live in adom-aiflow 0.2.60, with adom-aiflow-jlcpcb 0.1.4. Upgrade with adom-wiki pkg install adom/adom-aiflow and adom-wiki pkg install adom/adom-aiflow-jlcpcb.

You were right that export presented its BOM and CPL as if they were order files. They're AI Flow's review files: they're checked against the board, but they use KiCad's rotations and origins. Now:

  • export says in its answer that <board>-bom.csv and <board>-cpl.csv are for review and not a fab's upload format. It writes manufacturing/ORDER-FILES.md, which says which fab each file is for (your item 4).
  • Its first hints give the ordering command with your run's board and sourcing BOM filled in: for JLCPCB, adom-aiflow-jlcpcb init --board <board> --bom <sourcing BOM> --target <desktop>, then adom-aiflow-jlcpcb next. That stage covers your items 1 to 3:
    • It writes <board>-bom-jlcpcb.csv (Comment, Designator, Footprint, LCSC Part #) and <board>-cpl-jlcpcb.csv (Designator, Mid X, Mid Y, Layer, Rotation).
    • It fits each part's rotation and centroid to JLCPCB's own EasyEDA footprint, so your D1, D4, J1/J2 and J7 cases get corrected.
    • It refuses a placed part with no LCSC number.
  • adom-aiflow-jlcpcb 0.1.4 reads AI Flow's BOM columns as they are (Reference, MPN, LCSC Part # and so on, in any case). It also no longer takes a Mouser vendor_pn as an LCSC number. When sourcing isn't closed, it names each missing part by its MPN.

MPN searches that miss LCSC's listing without hyphens (EEE-FK1H101P vs EEEFK1H101P) are tracked on adom/adom-jlcpcb#3.

If your jlcpcb_files.py gets something right that the JLCPCB stage gets wrong on your board, please send it as a PR to adom/adom-aiflow-jlcpcb with the board that shows it. Your RMS-residual fit and the stock check are both good candidates.

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