AI Flow
Public Made by Adomby adom
Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board.
Stage dependency invalidation and owner-review loops after a failed engineering gate
Workflow regression: failed engineering gates leave a later stage active and repeat owner-review stops
Component: ADOM AI Flow stage sequencing / continuation hook / finish guard.
Affected versions: observed with a locally pinned 0.2.x build; verify against current upstream before fixing.
Scope: generic stage transitions for all boards and all supported EDA lanes.
Reproduction pattern
- Complete routing, pours and an outline-related step.
- A new spec rule or native analysis invalidates the previously accepted routing or placement evidence.
- The route/gate reports failure, with a concrete measured violation that requires a placement or rerouting change.
- The current stage continues to display the later outline step rather than the earliest stage invalidated by the failure.
- An owner-review stop artifact is written, but the finish/continuation hook does not receive that stop-evidence path; it keeps asking for the work to proceed.
- The agent repeats the same request for the owner to decide between an engineering relayout and a rule-budget change, even when the agent already owns normal layout engineering.
Observed incorrect behavior
The timeline accumulates time under the wrong stage, the stage is shown as current despite failed prerequisites, and the agent can settle into an idle review loop. The route may have zero DRC/unconnected errors yet still fail a valid higher-level electrical rule, so the acceptance reason must be preserved rather than discarded.
Expected generic behavior
- Record upstream dependency invalidation as a structured, immutable event bound to board/spec hashes and the exact checker result.
- Deterministically return to the earliest affected stage (usually placement for placement changes; routing for routing-only defects). Mark dependent later stages needs revalidation, not passed; retain historical evidence and time attribution.
- Distinguish real owner-only decisions (changes to frozen electrical budgets, purchases, privacy permissions, externally required approvals) from routine engineering authority explicitly delegated to the agent (placement, safe rerouting, copper changes within frozen limits).
- The agent should choose a technically valid engineering relayout autonomously, with preflight/dry-run, native DRC and rollback on failure; never silently relax a frozen length/current/thermal/safety requirement.
- The completion hook should read persisted stop evidence automatically (or pass its path explicitly), distinguish genuine blocked conditions from recoverable engineering work and avoid repeated prompts on the same unchanged blocker fingerprint.
- Separate stage elapsed time into active design, tool execution, blocked owner hold, media processing and unobserved idle; no fictional progress.
- Resume from a saved native board authority and maintain idempotent crash/restart handling.
Acceptance tests
- Stage N failure invalidates a prerequisite at Stage K: pointer returns to K, dependent stages are marked revalidation, and ledger preserves N's history.
- Check failure caused by legal placement change: agent is allowed to relayout and revalidate, without human signoff, when engineering authority was previously delegated.
- Frozen rule violation: no auto-amend or downgrade, and gate remains failed until board passes.
- Owner-only decisions: bounded, evidence-backed stop is honoured exactly once across future hook invocations; no spam loop.
- Completion hook receives/locates stop evidence after restart.
- No rewriting of historic stage timing; accurate attribution of each operation and state.
- Multi-board/multi-run and 25-stage generality; no project names, net names, component positions or design-specific hardcoding.
This is a separate workflow-control issue from the media-encoding defect. They share a user-visible symptom (a long-running stage) but require distinct patches and independent regression tests. No proprietary design details, board files, credentials, or unpublished circuitry are included.
Related issue: https://wiki.adom.inc/adom/adom-aiflow/issues/170 (separate media pipeline bottleneck).