gate ignores the planned pours: a pour-only power net (one-layer board) reads as hundreds of unconnected pads

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noah · 8d ago ·closed by John Lauer

Version: adom-aiflow 0.2.56 (local build 0.2.56+noah.1), KiCad 10.0.6 kicad-cli in the container, task-owned KiCad 10.0.4 editor on Windows 11.

What I ran: on a one-copper-layer board (all copper on F.Cu, no vias, +5V and GND reach every pad only through two F.Cu pours), pour then gate --plan aiflow/plan-route-ai.json.

What happened: OK: pours planned: 2 zones (0 keepouts), 0 vias, then the gate says FINDINGS (suggestions, nothing is blocked): gate failed: 0 new DRC errors, 375 unconnected (inherited 0) and lists GND and +5V pads such as ["PTH pad 1 [GND] of MP3","PTH pad 1 [GND] of MP1"]. The routed board the gate checks (<run>/board-routed.kicad_pcb) has only the board's own rule areas: the planned pours from plan-pours.json are not in it, so every pad the pours join reads as unconnected.

Expected: the gate fills the planned pours (plan-pours.json) before its DRC, or leaves pads that the planned pours join out of the unconnected count, so a board whose power nets are pour-only can pass the gate before land pours.

Repro: noah/adam-telle-nameplate run (private), rev B: design/single_layer.py --proof builds the same board offline with the pours filled and kicad-cli DRC reports 0 unconnected; the gate on the same plan reports 375.

Workaround: land the route anyway (the gate is a suggestion) and check unconnected after land pours.

1 Reply

John Lauer · 5d ago

Thanks Noah, the diagnosis in your issue was spot on.

What was wrong. gate builds its copy of the board (board-routed.kicad_pcb) from the run's board plus the routing plan, and nothing else. The pours that pour had planned in plan-pours.json were not in it, so on your one-layer board, where +5V and GND reach their pads only through the two F.Cu pours, KiCad's DRC saw every one of those pads as unconnected: 375 items that the real board, once poured, does not have.

What changed in adom-aiflow 0.2.58. When the run has a pour plan, gate adds the planned pours that the board does not carry yet to its copy, and the planned vias from plan-vias.json to the plan it checks. DRC fills them (KiCad's own refill with a native kicad-cli, the gate's raster fill otherwise), so the pads the pours join count as connected. A planned zone is skipped when the board already has a zone of that net on that layer (after land pours), and a planned via when the board already has one there, so nothing is added twice. Keepouts are not added. gate.json says what was added under plannedPours (zones, vias, nets). Nothing changes for a run with no pour yet.

How it was verified. A unit test checks that the planned zones (including an outline zone) go into the gate copy once, that a board which already has them gets nothing added, and that planned vias join the plan. A new workflow suite (tests/sides-pours-workflow.py) runs your case on a one-layer board with a fake DRC that reports pour-only pads as unconnected while no zone is present: gate before pour reports the unconnected pads as a finding, and gate after pour passes with 0 unconnected and both zones in the gate copy. I did not rerun your private nameplate board.

Still open. Nothing on the gate side. As before, land pours is still where the pours become real copper, and finish checks the live board.

Upgrade: tell your AI "give me the latest adom-aiflow" (or adom-wiki pkg install adom/adom-aiflow); adom-aiflow --version says 0.2.58.

John Lauer closed this · 5d ago