AI Flow

Rank the signals before placement and routing, then place and route in that order

Seen on: adom-aiflow 0.2.44 (AM32 ESC run, adom/am32-esc-2s6s-molecule). The same ranking applies to any board.

What happened: nothing in the flow asks the AI to decide which signals matter most on this board. route orders nets by length (shortest first in v1, longest first in a variant), with only the spec's decoupling pairs routed ahead. spec.placement (#53), impedanceTargets (#52) and planeUnder each capture one constraint, but nothing ranks them against each other.

On the ESC the results were:

• The gate-drive traces (driver pin through the gate resistor to the FET gate; the highest di/dt signals after the power loop) were 23 to 47 mm, 33 mm on average.
• The back-EMF sense lines (the analogue signals AM32's zero-crossing detection depends on) were 47 to 92 mm, two of the three about 90 mm across the board.
• Debug and telemetry lines got similar treatment.

On the hand-routed board the gate-drive traces are 15 to 29 mm (22 mm on average), the back-EMF lines 17 to 32 mm, and the MCU-to-driver PWM lines about 2 mm (numbers in #128).

How a layout engineer works: rank first. On a board with high-speed USB and a 9600-baud UART, USB comes first: it needs impedance control and a differential pair, and it is far more sensitive to routing errors. You place and route for USB, then make the UART fit. Highest speed, most sensitive and highest power go first. It is the AI's job to make that ranking for each board and say why.

Suggested fix:

1. A ranking written before placement, as spec.signalPriority: an ordered list of classes, each with its nets and a one-line reason. For example:

   [{"class":"power loop","nets":["VBAT","PH*","GND"],"why":"20 A, sets heat and EMI"},
    {"class":"gate drive","nets":["GH*","GL*","SH*"],"why":"highest di/dt, ringing"},
    {"class":"BEMF sense","nets":["BEMF_*","NEUTRAL"],"why":"analogue zero-crossing"},
    {"class":"PWM","nets":["INH*","INL*"],"why":"timing"},
    {"class":"slow","nets":["SWD*","TLM","SIG"],"why":"kHz or static"}]
   

   The design or placement step requires it, and finish refuses a run without one (or with an explicit deviation). The timeline shows it.

2. Placement uses it. place check reports each top-class loop or ratsnest length and area. The place pack wish order follows the ranking.

3. Routing uses it. route routes classes in rank order, top class first, and rips up lower classes before higher ones. The class sets the defaults:

   • via budget
   • geometry strictness (#127)
   • width
   • planeUnder or reference-plane rule

4. Gate and finish report per class: "gate drive: 6 lines, worst GHA 47 mm, 2 vias (budget 0)".

5. The aiflow-power-layout and kicad-place-route-loop skills already teach this judgement for power boards. Moving it into a spec field the binary reads makes it apply to every board.

Related: #127 (route geometry), #128 (vias and detours), #130 (placement priorities).