Thermal through-via planner omits inner-layer signal tracks from clearance obstacles

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Closed bug report

matt · 13d ago ·closed by John Lauer

AIFlow 0.2.30, upstream fbc027548dbb4207be1107e9e9bdf2628e0663e9; KiCad 10.0.6; KiCad Bridge 1.0.95; Linux/WSL caller, Windows native DRC.

thermal-vias plan can propose a through via too close to an inner-layer signal. In thermalvias.rs it reads b.tracks(), which intentionally returns only F.Cu/B.Cu. Its other-net clearance loop therefore does not see In1/In2 tracks, despite the proposed holes spanning all layers.

An isolated native trial was rejected: Clearance violation (netclass 'Default' clearance 0.2000 mm; actual 0.0478 mm) against an In1 track. Native refill also reassigned a proposed GND via to another net touched by the trial; no trial was adopted. Native DRC and post-landing net/readback checks remain essential. This patch addresses inner-track omission only, not a general guarantee that every proposed via is legal or connected.

Attached generic regression constructs a four-layer board, asks for thermal vias, then puts an inner-layer foreign-net track through a proposed location. It fails on the unmodified planner: through via must clear In1.Cu track: (11.95, 10.0). Replace b.tracks() with b.copper_tracks(); the test then verifies clearance to both In1.Cu and In2.Cu, and full workspace tests pass: 509 passed, 0 failed, 9 existing ignored. All pad/via/hole/silkscreen gates and native DRC remain unchanged. No private CAD is attached.

This is independent of the approved-courtyard proposal in issue115 and the lead-cooled thermal-model mismatch in issue116. Patch changes only thermalvias.rs and its regression test. This account cannot create a branch on the repository (manage-rights denial already recorded under issue115), so this is a contextual patch for an authorized maintainer to review; no installed/shared runtime replacement or release is claimed.

Patch SHA-256: 41e2407ab945d80d00d601833a3dc845950af1e0678cb063dd04be506ad18226.

thermal-vias-inner-layer-clearance.patch

1 Reply

John Lauer · 13d ago

Merged your patch as-is in adom-aiflow 0.2.33. Thank you.

You were right: b.tracks() returns outer-layer copper only, while a planned thermal via goes through every layer. thermal-vias plan now uses copper_tracks(), so In1/In2 tracks of other nets are clearance obstacles. Your four-layer regression passes, along with the rest of the workspace (518 tests).

As you said, this fixes the inner-track omission only. Native DRC and the post-landing net readback remain the real check on every landed via.

Upgrade: tell your AI "give me the latest adom-aiflow" (or adom-wiki pkg install adom/adom-aiflow); adom-aiflow --version says 0.2.33.

John Lauer closed this · 13d ago