AI Flow

@@ -380,6 +380,7 @@ Every clip stop runs a blank check (eight frames sampled in one decode pass; a c - A stage you take yourself is stamped by you and named in the manifest as `ai`; the binary's stages are `binary`. Both go on the chart. - `finish` is the only thing that ends a run. A run without `finish` is not a result, and its minutes are still counting. - KiCad drops pour islands that touch nothing: a heat spreader drawn across dense routing on the other layer fills as fragments and reads small in `measure`. Put the copper where the layer is actually free (the analysis numbers say when it is not).+- Keep the copper (Drew, 2026-11-14, every board): the 3rd party fab ablates whatever copper the board does not keep, so fill the free area with GND on both layers and remove no island silently. Tie each orphan to GND on its own layer or widen the adjacent trace into the gap (a new via only when the island is worth a hole), leave copper out only where its absence is the feature (mutual coupling, high-impedance analog inputs, RF and antenna keep-outs, controlled-impedance spacing, the switch node) as a named keepout, and report the copper kept and the area left to ablate before and after. Read `docs/keep-copper.md`. - 0.1's analyses are conservative heuristics (IPC-2221 for tracks, presence, connection style and vias for pours and tabs); they say so in their output. 0.2 computes cross-sections through the filled copper.  ## Evidence comes from the work (0.1.93)

@@ -0,0 +1,41 @@+# Keep the copper: the 3rd party fab's DFM rule for pours++Drew's rule (2026-11-14), for every board:++> For all boards, note that Adom's process starts with a full copper plane and has to ablate the copper bit by bit, so leave as much copper as possible. Where there would be an orphan section of copper, tie it to ground or widen adjacent traces to fill the gap. The one exception would be where electrical performance (e.g. mutual coupling) would degrade by leaving copper. In such cases, the absence of copper is a feature in itself, not just a convenience.++## Why++The 3rd party fab starts from a fully clad board and removes copper with a laser. Every square millimetre the board keeps is a square millimetre the laser does not remove, so the ablated area is line time. On this process a pour is the cheapest copper on the board, and `measure` reports the copper kept per layer for that reason.++Holes are line time too. Every via is a hole the laser drills, and drilling is slow, so a new via that saves a small island usually costs more line time than the copper it keeps. Keep copper with the copper and vias the board already has, not with new holes.++## How AI Flow applies it++1. **Fill the free area with GND on both layers.** Every area no other net needs gets a GND pour (a `spec.pours` entry on `F.Cu` and `B.Cu` over the board outline). Other nets' pours win inside it by priority, as before.+2. **Remove no island silently.** KiCad's fill drops copper that connects to nothing of its net (`islandRemoval: always`, the only mode `land pours` can land), so an orphan shows up as an empty pocket in the pour and its copper is ablated. Find them: look at the landed pour for pockets, or fill a copy of the board offline with island removal set to never (pcbnew Python) and compare it with the landed fill; every extra polygon is an orphan. Fix each one, in this order:+   - **Tie it to GND on its own layer.** Move or re-route the trace that cuts it off, so a neck at least the pour's `minThickness` wide reaches it.+   - **Or widen the adjacent trace into the gap.** Add a small `spec.pours` zone of that trace's net over the pocket, at a higher priority than GND. Do this only where extra copper is harmless for that net (power, ground, slow logic; see the exceptions below).+   - **A new via to GND on the other layer** only when neither works and the island is big enough to be worth a hole.+   - **Otherwise leave it ablated and list it**, with its layer, its area and the reason.++   Floating copper is not the fix: copper with no net has an uncontrolled potential.+3. **Prefer no new vias.** A stitching via is there for an electrical reason (a return path, a plane tie, heat), not to rescue a sliver of copper.+4. **Report the copper.** Per layer, give the copper kept and the area left to ablate (the board area minus the copper kept), after the first fill and again after the island fixes. `land pours` prints the copper per layer before and after, and `measure` gives the coverage. Also say how many orphans were tied to GND, merged into a trace, given a via, or left out, and why.++## The exceptions: where no copper is the feature++Leave copper out on purpose where it would hurt the circuit, and record the decision as a named net-less keepout in `spec.pours`, so that nobody fills it later:++```json+{"name": "no copper: antenna keep-out (module datasheet)", "keepout": {"copperPour": true}, "layers": ["F.Cu", "B.Cu"], "polygon": [[x1, y1], [x2, y1], [x2, y2], [x1, y2]]}+```++- **Mutual coupling.** Coils, transformer windings, inductive or capacitive sensors, and the traces that must not couple to them. Copper nearby changes the coupling or carries eddy currents.+- **High-impedance analog inputs.** Feedback nodes, sense inputs, op-amp inputs and oscillator pins. Extra copper adds capacitance and leakage.+- **RF and antenna keep-outs.** The antenna's clearance area on every layer, as its datasheet draws it.+- **Controlled-impedance spacing.** The gap beside an impedance-controlled trace or pair is part of its impedance. Do not fill it, and do not widen the trace.+- **Switch-node areas.** Keep the SW copper as small as the current allows, and never widen it into a gap: a bigger SW patch is a bigger antenna. The ground under the hot loop stays.+- The keepouts AI Flow already makes (Kelvin sense taps), and any isolation gap that a voltage needs.++This refines eda-copper-ablation (adom/eda-engineering) for AI Flow runs. That skill keeps floating islands when the human asks for them; here an orphan is tied to ground or merged into a trace instead.

@@ -179,7 +179,10 @@         "land pours",         "measure"       ],-      "record": "the pours filling in (land pours) and the copper readback; keep the DRC refusals in the clip, they are the story"+      "record": "the pours filling in (land pours) and the copper readback; keep the DRC refusals in the clip, they are the story",+      "workflow": [+        "Keep the copper (Drew, 2026-11-14, every board; docs/keep-copper.md): the 3rd party fab ablates whatever copper the board does not keep, so pour GND over the free area on both layers and remove no island silently: tie each orphan to GND on its own layer or widen the adjacent trace into the gap, and add a new via only when the island is worth a hole. Leave copper out only where its absence is the feature (mutual coupling, high-impedance analog inputs, RF and antenna keep-outs, controlled-impedance spacing, the switch node), as a named keepout in spec.pours. Report the copper kept and the area left to ablate per layer, before and after."+      ]     },     {       "name": "outline",

@@ -474,6 +474,7 @@ Every clip stop runs a blank check (eight frames sampled in one decode pass; a c - A stage you take yourself is stamped by you and named in the manifest as `ai`; the binary's stages are `binary`. Both go on the chart. - `finish` is the only thing that ends a run. A run without `finish` is not a result, and its minutes are still counting. - KiCad drops pour islands that touch nothing: a heat spreader drawn across dense routing on the other layer fills as fragments and reads small in `measure`. Put the copper where the layer is actually free (the analysis numbers say when it is not).+- Keep the copper (Drew, 2026-11-14, every board): the 3rd party fab ablates whatever copper the board does not keep, so fill the free area with GND on both layers and remove no island silently. Tie each orphan to GND on its own layer or widen the adjacent trace into the gap (a new via only when the island is worth a hole), leave copper out only where its absence is the feature (mutual coupling, high-impedance analog inputs, RF and antenna keep-outs, controlled-impedance spacing, the switch node) as a named keepout, and report the copper kept and the area left to ablate before and after. Read `docs/keep-copper.md`. - 0.1's analyses are conservative heuristics (IPC-2221 for tracks, presence, connection style and vias for pours and tabs); they say so in their output. 0.2 computes cross-sections through the filled copper.  ## Spec intent checked by the binary (0.2.3)