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ADF4351BCPZ
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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# ADF4351BCPZ++**Analog Devices** · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-32(5x5)++ADF4351BCPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLK | input | Serial clock input; 32-bit data is input bit-by-bit to shift register on CLK rising edge; high impedance CMOS input. |+| 2 | DATA | input | Serial data input; data loaded MSB first with three LSBs serving as control bits C3, C2, C1; high impedance CMOS input. |+| 3 | LE | input | Load enable input; when LE transitions high, data from 32-bit shift register loads into register selected by control bits; high impedance CMOS input. |+| 4 | CE | input | Chip enable input; logic low powers down device and puts charge pump into tri-state; logic high powers up device based on shutdown bit state. |+| 5 | SW | output | Fast lock switch output; external loop filter connected to this pin when using fast lock mode; SW pin can be shorted to AGND during fast lock. |+| 6 | VP | power_in | Charge pump supply voltage; must equal AVDD (3.0 V to 3.6 V); place decoupling capacitor close to this pin. |+| 7 | CPOUT | output | Charge pump output; provides ±ICP (0.312 mA to 5.0 mA programmable) to external loop filter when enabled; loop filter output connects to VTUNE. |+| 8 | CPGND | power_in | Charge pump ground return; ground reference for CPOUT output. |+| 9 | AGND | power_in | Analog ground; ground reference return for AVDD analog supply voltage. |+| 10 | AVDD | power_in | Analog supply voltage; 3.0 V to 3.6 V; must equal DVDD; place decoupling capacitor close to this pin. |+| 11 | AGNDVCO | power_in | VCO analog ground; ground return for VCO core circuit. |+| 12 | RFOUTA+ | output | VCO fundamental (2.2 GHz to 4.4 GHz) or divided output (34.375 MHz min); programmable power −4 dBm to +5 dBm in 3 dB steps. |+| 13 | RFOUTA- | output | Complementary VCO output; provides VCO fundamental or divided output; programmable power −4 dBm to +5 dBm. |+| 14 | RFOUTB+ | output | Auxiliary VCO output; provides VCO fundamental or divided output; programmable power −4 dBm to +5 dBm; disabled when not needed. |+| 15 | RFOUTB- | output | Complementary auxiliary VCO output; provides VCO fundamental or divided output; programmable power −4 dBm to +5 dBm. |+| 16 | VVCO | power_in | VCO supply voltage; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin. |+| 17 | VVCO | power_in | VCO supply voltage; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin. |+| 18 | AGNDVCO | power_in | VCO analog ground; ground return for VCO core circuit. |+| 19 | TEMP | output | Temperature compensation output; provides temperature-compensated bias for optimizing VCO performance; place decoupling capacitor close to pin. |+| 20 | VTUNE | input | VCO tuning control input; voltage derived from filtered CPOUT determines VCO output frequency; control range 0.5 V to 2.5 V. |+| 21 | AGNDVCO | power_in | VCO analog ground; ground return for VCO core circuit. |+| 22 | RSET | output | Charge pump current setting pin; connect resistor between RSET and ground to program ICP; nominal bias voltage 0.55 V; ICP = 25.5/RSET(kΩ); RSET range 3.9 kΩ to 10 kΩ. |+| 23 | VCOM | output | Internal compensation node; biases half the tuning range of VCO; place decoupling capacitor close to this pin. |+| 24 | VREF | power_in | Reference voltage output; provides bias references for analog circuits; place decoupling capacitor close to this pin. |+| 25 | LD | output | Lock detect output; outputs logic high when PLL locked; outputs logic low when PLL unlocked; pin mode configurable via register 5. |+| 26 | PDBRF | input | RF power down control input; logic low mutes RF outputs RFOUTA and RFOUTB; logic high enables RF output; also software programmable. |+| 27 | DGND | power_in | Digital ground; ground return for DVDD digital supply voltage. |+| 28 | DVDD | power_in | Digital supply voltage; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin. |+| 29 | REFIN | input | Reference clock input; 10 MHz to 250 MHz; CMOS input with nominal threshold at AVDD/2; 100 kΩ input resistance; TTL/CMOS oscillator or AC-coupled. |+| 30 | MUXOUT | tri_state | Multiplexer output; provides access to lock detect, N divider output, R divider output, or supply voltages; configurable via M3:M1 bits in register 2. |+| 31 | SDGND | power_in | Digital sigma-delta modulator ground; ground return for Σ-Δ modulator circuits. |+| 32 | SDVDD | power_in | Digital sigma-delta modulator supply; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-32(5x5) |+| Category | Clock/Timing |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `ADF4351BCPZ`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)+- 3D model files: `adf4351bcpz-etched.step` / `adf4351bcpz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adf4351bcpz.step` / `adf4351bcpz.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915074786603008) (28 pp, sha256 `bf842820730b1137`, retrieved 2026-09-21, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adf4351bcpz-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "adf4351bcpz",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adf4351bcpz.kicad_sym",+ "adf4351bcpz.kicad_mod",+ "adf4351bcpz.glb",+ "adf4351bcpz.step",+ "adf4351bcpz.lbr",+ "docs/hero.png",+ "docs/adf4351bcpz-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADF4351BCPZ",+ "manufacturer": "Analog Devices",+ "package": "LFCSP-32(5x5)",+ "pin_count": 33,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915074786603008",+ "parts": {+ "symbol": "adf4351bcpz.kicad_sym",+ "footprint": "adf4351bcpz.kicad_mod",+ "model_3d": "adf4351bcpz-etched.glb",+ "model_3d_plain": "adf4351bcpz.glb",+ "model_3d_step": "adf4351bcpz-etched.step",+ "model_3d_step_plain": "adf4351bcpz.step",+ "lbr": "adf4351bcpz.lbr"+ },+ "distributor_links": {+ "lcsc": "C654681"+ },+ "pins": [+ {+ "number": "1",+ "name": "CLK",+ "type": "input",+ "description": "Serial clock input; 32-bit data is input bit-by-bit to shift register on CLK rising edge; high impedance CMOS input."+ },+ {+ "number": "2",+ "name": "DATA",+ "type": "input",+ "description": "Serial data input; data loaded MSB first with three LSBs serving as control bits C3, C2, C1; high impedance CMOS input."+ },+ {+ "number": "3",+ "name": "LE",+ "type": "input",+ "description": "Load enable input; when LE transitions high, data from 32-bit shift register loads into register selected by control bits; high impedance CMOS input."+ },+ {+ "number": "4",+ "name": "CE",+ "type": "input",+ "description": "Chip enable input; logic low powers down device and puts charge pump into tri-state; logic high powers up device based on shutdown bit state."+ },+ {+ "number": "5",+ "name": "SW",+ "type": "output",+ "description": "Fast lock switch output; external loop filter connected to this pin when using fast lock mode; SW pin can be shorted to AGND during fast lock."+ },+ {+ "number": "6",+ "name": "VP",+ "type": "power_in",+ "description": "Charge pump supply voltage; must equal AVDD (3.0 V to 3.6 V); place decoupling capacitor close to this pin."+ },+ {+ "number": "7",+ "name": "CPOUT",+ "type": "output",+ "description": "Charge pump output; provides ±ICP (0.312 mA to 5.0 mA programmable) to external loop filter when enabled; loop filter output connects to VTUNE."+ },+ {+ "number": "8",+ "name": "CPGND",+ "type": "power_in",+ "description": "Charge pump ground return; ground reference for CPOUT output."+ },+ {+ "number": "9",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; ground reference return for AVDD analog supply voltage."+ },+ {+ "number": "10",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage; 3.0 V to 3.6 V; must equal DVDD; place decoupling capacitor close to this pin."+ },+ {+ "number": "11",+ "name": "AGNDVCO",+ "type": "power_in",+ "description": "VCO analog ground; ground return for VCO core circuit."+ },+ {+ "number": "12",+ "name": "RFOUTA+",+ "type": "output",+ "description": "VCO fundamental (2.2 GHz to 4.4 GHz) or divided output (34.375 MHz min); programmable power −4 dBm to +5 dBm in 3 dB steps."+ },+ {+ "number": "13",+ "name": "RFOUTA-",+ "type": "output",+ "description": "Complementary VCO output; provides VCO fundamental or divided output; programmable power −4 dBm to +5 dBm."+ },+ {+ "number": "14",+ "name": "RFOUTB+",+ "type": "output",+ "description": "Auxiliary VCO output; provides VCO fundamental or divided output; programmable power −4 dBm to +5 dBm; disabled when not needed."+ },+ {+ "number": "15",+ "name": "RFOUTB-",+ "type": "output",+ "description": "Complementary auxiliary VCO output; provides VCO fundamental or divided output; programmable power −4 dBm to +5 dBm."+ },+ {+ "number": "16",+ "name": "VVCO",+ "type": "power_in",+ "description": "VCO supply voltage; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin."+ },+ {+ "number": "17",+ "name": "VVCO",+ "type": "power_in",+ "description": "VCO supply voltage; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin."+ },+ {+ "number": "18",+ "name": "AGNDVCO",+ "type": "power_in",+ "description": "VCO analog ground; ground return for VCO core circuit."+ },+ {+ "number": "19",+ "name": "TEMP",+ "type": "output",+ "description": "Temperature compensation output; provides temperature-compensated bias for optimizing VCO performance; place decoupling capacitor close to pin."+ },+ {+ "number": "20",+ "name": "VTUNE",+ "type": "input",+ "description": "VCO tuning control input; voltage derived from filtered CPOUT determines VCO output frequency; control range 0.5 V to 2.5 V."+ },+ {+ "number": "21",+ "name": "AGNDVCO",+ "type": "power_in",+ "description": "VCO analog ground; ground return for VCO core circuit."+ },+ {+ "number": "22",+ "name": "RSET",+ "type": "output",+ "description": "Charge pump current setting pin; connect resistor between RSET and ground to program ICP; nominal bias voltage 0.55 V; ICP = 25.5/RSET(kΩ); RSET range 3.9 kΩ to 10 kΩ."+ },+ {+ "number": "23",+ "name": "VCOM",+ "type": "output",+ "description": "Internal compensation node; biases half the tuning range of VCO; place decoupling capacitor close to this pin."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_in",+ "description": "Reference voltage output; provides bias references for analog circuits; place decoupling capacitor close to this pin."+ },+ {+ "number": "25",+ "name": "LD",+ "type": "output",+ "description": "Lock detect output; outputs logic high when PLL locked; outputs logic low when PLL unlocked; pin mode configurable via register 5."+ },+ {+ "number": "26",+ "name": "PDBRF",+ "type": "input",+ "description": "RF power down control input; logic low mutes RF outputs RFOUTA and RFOUTB; logic high enables RF output; also software programmable."+ },+ {+ "number": "27",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground; ground return for DVDD digital supply voltage."+ },+ {+ "number": "28",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply voltage; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin."+ },+ {+ "number": "29",+ "name": "REFIN",+ "type": "input",+ "description": "Reference clock input; 10 MHz to 250 MHz; CMOS input with nominal threshold at AVDD/2; 100 kΩ input resistance; TTL/CMOS oscillator or AC-coupled."+ },+ {+ "number": "30",+ "name": "MUXOUT",+ "type": "tri_state",+ "description": "Multiplexer output; provides access to lock detect, N divider output, R divider output, or supply voltages; configurable via M3:M1 bits in register 2."+ },+ {+ "number": "31",+ "name": "SDGND",+ "type": "power_in",+ "description": "Digital sigma-delta modulator ground; ground return for Σ-Δ modulator circuits."+ },+ {+ "number": "32",+ "name": "SDVDD",+ "type": "power_in",+ "description": "Digital sigma-delta modulator supply; 3.0 V to 3.6 V; must equal AVDD; place decoupling capacitor close to this pin."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: SW pin classification: Described as 'Fast Lock Switch' with external loop filter connection; classif; RSET pin classification: Provides 0.55 V bias voltage for external resistor setting charge pump curr; VCO Analog Ground (AGNDVCO) appears at pins 11, 18, and 21; all classified as power_in as ground con",+ "exposed pad 33 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 28,+ "cost_usd": 0.662,+ "at": "2026-09-21T20:45:47"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915074786603008",+ "pages": 28,+ "sha256": "bf842820730b1137",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}