component
ADF4159CCPZ-RL7
Public Made by Adomby adom
Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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adf4159ccpz-rl7: factory component page (tier=lcsc)
4 files changed
+76−75
README.md+25−25@@ -8,31 +8,31 @@ ADF4159CCPZ-RL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descript | Pin | Name | Type | Function | |---|---|---|---|-| 1 | CPGND | power_in | Charge Pump Ground; ground return path for the charge pump. |-| 2 | AGND | power_in | Analog Ground; analog ground reference. |-| 3 | AGND | power_in | Analog Ground; analog ground reference. |-| 4 | RFINB | input | Complementary RF input to the prescaler; decouple to ground plane with 100 pF bypass capacitor. |-| 5 | RFINA | input | RF input to the prescaler; small signal input normally AC-coupled from the VCO. |-| 6 | AVDD | power_in | Positive Power Supply for the RF Section (2.7-3.45 V); place decoupling capacitors to ground as close as possible. |-| 7 | AVDD | power_in | Positive Power Supply for the RF Section (2.7-3.45 V); place decoupling capacitors to ground as close as possible. |-| 8 | AVDD | power_in | Positive Power Supply for the RF Section (2.7-3.45 V); place decoupling capacitors to ground as close as possible. |-| 9 | REFIN | input | Reference Input; CMOS input with nominal threshold DVDD/2, equivalent input resistance 100 kΩ, accepts 10-260 MHz input. |-| 10 | DGND | power_in | Digital Ground; digital ground reference. |-| 11 | SDGND | power_in | Digital Σ-Δ Modulator Ground; ground return path for the Σ-Δ modulator. |-| 12 | TXDATA | input | Transmit Data Pin; provides data for FSK or PSK modulation and controls ramping functionality. |-| 13 | CE | input | Chip Enable (1.8 V logic); logic low powers down device and places charge pump into three-state mode. |-| 14 | CLK | input | Serial Clock Input; high impedance CMOS input used to clock serial data into registers with data latched on rising edge. |-| 15 | DATA | input | Serial Data Input; high impedance CMOS input, loaded MSB first with three LSBs as control bits. |-| 16 | LE | input | Load Enable Input; high impedance CMOS input; when high, transfers data from shift register to selected latch. |-| 17 | MUXOUT | tri_state | Multiplexer Output; three-state output allowing access to various internal signals. |-| 18 | SDVDD | power_in | Power Supply for the Digital Σ-Δ Modulator (1.8 V); place decoupling capacitors to ground as close as possible. |-| 19 | DVDD | power_in | Positive Power Supply for the Digital Section (1.8 V); place decoupling capacitors to ground as close as possible. |-| 20 | SW1 | output | Switch for Fast Lock; shorted to ground internally during fast lock operation for charge pump current boost. |-| 21 | SW2 | output | Switch for Fast Lock; connected to charge pump output internally during fast lock operation. |-| 22 | VP | power_in | Charge Pump Power Supply (2.7-3.45 V); must be ≥ AVDD. |-| 23 | RSET | passive | Charge Pump Current Setting; connect resistor to ground (4.59-5.61 kΩ) with ICP_MAX = 24.48/RSET. |-| 24 | CP | output | Charge Pump Output; when enabled provides ±ICP to external loop filter driving the VCO. |-| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |+| 1 | CPGND | power_in | Charge pump ground return that provides the ground reference path for the charge pump circuit. |+| 2 | AGND | power_in | Analog ground reference for the RF and analog signal processing circuitry. |+| 3 | AGND | power_in | Analog ground reference for the RF and analog signal processing circuitry. |+| 4 | RFINB | input | Complementary RF prescaler input requiring a 100 pF bypass capacitor to ground plane. |+| 5 | RFINA | input | AC-coupled RF prescaler input accepting 0.5 to 13 GHz signals at −10 to 0 dBm with minimum 400 V/µs slew rate. |+| 6 | AVDD | power_in | Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin. |+| 7 | AVDD | power_in | Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin. |+| 8 | AVDD | power_in | Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin. |+| 9 | REFIN | input | Reference input accepting 10 to 260 MHz CMOS signal at −5 to +9 dBm with 100 kΩ input impedance. |+| 10 | DGND | power_in | Digital ground providing reference for logic and digital signal processing circuitry. |+| 11 | SDGND | power_in | Sigma-delta modulator ground providing return path for the Σ-Δ fractional interpolator circuit. |+| 12 | TXDATA | input | Transmit data input for FSK and PSK modulation control and ramp step triggering signals. |+| 13 | CE | input | Active-low chip enable input that powers down device and places charge pump into three-state mode. |+| 14 | CLK | input | Serial clock input for shifting 32-bit data words into the input shift register on rising clock edges. |+| 15 | DATA | input | Serial data input receiving MSB-first data with control bits in three LSBs at high impedance. |+| 16 | LE | input | Load enable input that latches 32-bit word from shift register into target register on rising edge. |+| 17 | MUXOUT | tri_state | Three-state multiplexer output providing access to internal signals including lock detect, divider outputs, and frequency readback. |+| 18 | SDVDD | power_in | Positive 1.8 V power supply for Σ-Δ modulator with decoupling capacitors required close to pin. |+| 19 | DVDD | power_in | Positive 1.62 to 1.98 V digital power supply for logic circuits with decoupling capacitors required close to pin. |+| 20 | SW1 | passive | Fast lock mode switch pin that is shorted to ground to modify loop filter resistance during wideband lock operation. |+| 21 | SW2 | passive | Fast lock mode switch pin that is connected to charge pump output for loop stabilization during wideband lock operation. |+| 22 | VP | power_in | Charge pump power supply accepting 2.7 to 3.45 V with requirement that VP ≥ AVDD. |+| 23 | RSET | passive | External resistor connection to ground for setting maximum charge pump current per ICP_MAX = 24.48 mA / RSET(kΩ). |+| 24 | CP | output | Charge pump output providing ±0.31 to 5.0 mA programmable current to external loop filter and VCO. |+| 25 | EPAD | power_in | Exposed thermal and electrical ground pad that must be soldered to AGND for proper heat dissipation. | ## Key specifications
adf4159ccpz-rl7.kicad_sym+4−4@@ -60,8 +60,8 @@ (name "CE" (effects (font (size 1.27 1.27)))) (number "13" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 12.70 180) (length 5.08)- (name "EP" (effects (font (size 1.27 1.27))))+ (pin power_in line (at 17.78 12.70 180) (length 5.08)+ (name "EPAD" (effects (font (size 1.27 1.27)))) (number "25" (effects (font (size 1.27 1.27)))) ) (pin output line (at 17.78 10.16 180) (length 5.08)@@ -76,11 +76,11 @@ (name "VP" (effects (font (size 1.27 1.27)))) (number "22" (effects (font (size 1.27 1.27)))) )- (pin output line (at 17.78 2.54 180) (length 5.08)+ (pin passive line (at 17.78 2.54 180) (length 5.08) (name "SW2" (effects (font (size 1.27 1.27)))) (number "21" (effects (font (size 1.27 1.27)))) )- (pin output line (at 17.78 0.00 180) (length 5.08)+ (pin passive line (at 17.78 0.00 180) (length 5.08) (name "SW1" (effects (font (size 1.27 1.27)))) (number "20" (effects (font (size 1.27 1.27)))) )
adf4159ccpz-rl7.lbr+14−7@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4)</description> <packages> <package name="QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm"> <description>QFN-24-1EP, 4 x 4 mm, 0.5 mm pitch</description>@@ -105,6 +105,7 @@ </packages> <symbols> <symbol name="ADF4159CCPZ-RL7">+ <description>Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4)</description> <wire x1="-12.7" y1="17.78" x2="12.7" y2="17.78" width="0.254" layer="94"/> <wire x1="12.7" y1="17.78" x2="12.7" y2="-17.78" width="0.254" layer="94"/> <wire x1="12.7" y1="-17.78" x2="-12.7" y2="-17.78" width="0.254" layer="94"/>@@ -124,12 +125,12 @@ <pin name="SDGND" x="-17.78" y="-10.16" length="middle" direction="pwr"/> <pin name="TXDATA" x="-17.78" y="-12.7" length="middle" direction="in"/> <pin name="CE" x="-17.78" y="-15.24" length="middle" direction="in"/>- <pin name="EP" x="17.78" y="12.7" length="middle" direction="pas" rot="R180"/>+ <pin name="EPAD" x="17.78" y="12.7" length="middle" direction="pwr" rot="R180"/> <pin name="CP" x="17.78" y="10.16" length="middle" direction="out" rot="R180"/> <pin name="RSET" x="17.78" y="7.62" length="middle" direction="pas" rot="R180"/> <pin name="VP" x="17.78" y="5.08" length="middle" direction="pwr" rot="R180"/>- <pin name="SW2" x="17.78" y="2.54" length="middle" direction="out" rot="R180"/>- <pin name="SW1" x="17.78" y="0" length="middle" direction="out" rot="R180"/>+ <pin name="SW2" x="17.78" y="2.54" length="middle" direction="pas" rot="R180"/>+ <pin name="SW1" x="17.78" y="0" length="middle" direction="pas" rot="R180"/> <pin name="DVDD" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/> <pin name="SDVDD" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/> <pin name="MUXOUT" x="17.78" y="-7.62" length="middle" direction="hiz" rot="R180"/>@@ -140,7 +141,7 @@ </symbols> <devicesets> <deviceset name="ADF4159CCPZ-RL7" prefix="U">- <description></description>+ <description>Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4)</description> <gates> <gate name="G$1" symbol="ADF4159CCPZ-RL7" x="0" y="0"/> </gates>@@ -160,7 +161,7 @@ <connect gate="G$1" pin="SDGND" pad="11"/> <connect gate="G$1" pin="TXDATA" pad="12"/> <connect gate="G$1" pin="CE" pad="13"/>- <connect gate="G$1" pin="EP" pad="25"/>+ <connect gate="G$1" pin="EPAD" pad="25"/> <connect gate="G$1" pin="CP" pad="24"/> <connect gate="G$1" pin="RSET" pad="23"/> <connect gate="G$1" pin="VP" pad="22"/>@@ -173,7 +174,13 @@ <connect gate="G$1" pin="DATA" pad="15"/> <connect gate="G$1" pin="CLK" pad="14"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="ADF4159CCPZ-RL7" constant="no"/>+ <attribute name="MANUFACTURER" value="Analog Devices" constant="no"/>+ <attribute name="LCSC_PN" value="C495333" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+33−39@@ -36,151 +36,151 @@ "number": "1", "name": "CPGND", "type": "power_in",- "description": "Charge Pump Ground; ground return path for the charge pump."+ "description": "Charge pump ground return that provides the ground reference path for the charge pump circuit." }, { "number": "2", "name": "AGND", "type": "power_in",- "description": "Analog Ground; analog ground reference."+ "description": "Analog ground reference for the RF and analog signal processing circuitry." }, { "number": "3", "name": "AGND", "type": "power_in",- "description": "Analog Ground; analog ground reference."+ "description": "Analog ground reference for the RF and analog signal processing circuitry." }, { "number": "4", "name": "RFINB", "type": "input",- "description": "Complementary RF input to the prescaler; decouple to ground plane with 100 pF bypass capacitor."+ "description": "Complementary RF prescaler input requiring a 100 pF bypass capacitor to ground plane." }, { "number": "5", "name": "RFINA", "type": "input",- "description": "RF input to the prescaler; small signal input normally AC-coupled from the VCO."+ "description": "AC-coupled RF prescaler input accepting 0.5 to 13 GHz signals at \u221210 to 0 dBm with minimum 400 V/\u00b5s slew rate." }, { "number": "6", "name": "AVDD", "type": "power_in",- "description": "Positive Power Supply for the RF Section (2.7-3.45 V); place decoupling capacitors to ground as close as possible."+ "description": "Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin." }, { "number": "7", "name": "AVDD", "type": "power_in",- "description": "Positive Power Supply for the RF Section (2.7-3.45 V); place decoupling capacitors to ground as close as possible."+ "description": "Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin." }, { "number": "8", "name": "AVDD", "type": "power_in",- "description": "Positive Power Supply for the RF Section (2.7-3.45 V); place decoupling capacitors to ground as close as possible."+ "description": "Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin." }, { "number": "9", "name": "REFIN", "type": "input",- "description": "Reference Input; CMOS input with nominal threshold DVDD/2, equivalent input resistance 100 kΩ, accepts 10-260 MHz input."+ "description": "Reference input accepting 10 to 260 MHz CMOS signal at \u22125 to +9 dBm with 100 k\u03a9 input impedance." }, { "number": "10", "name": "DGND", "type": "power_in",- "description": "Digital Ground; digital ground reference."+ "description": "Digital ground providing reference for logic and digital signal processing circuitry." }, { "number": "11", "name": "SDGND", "type": "power_in",- "description": "Digital Σ-Δ Modulator Ground; ground return path for the Σ-Δ modulator."+ "description": "Sigma-delta modulator ground providing return path for the \u03a3-\u0394 fractional interpolator circuit." }, { "number": "12", "name": "TXDATA", "type": "input",- "description": "Transmit Data Pin; provides data for FSK or PSK modulation and controls ramping functionality."+ "description": "Transmit data input for FSK and PSK modulation control and ramp step triggering signals." }, { "number": "13", "name": "CE", "type": "input",- "description": "Chip Enable (1.8 V logic); logic low powers down device and places charge pump into three-state mode."+ "description": "Active-low chip enable input that powers down device and places charge pump into three-state mode." }, { "number": "14", "name": "CLK", "type": "input",- "description": "Serial Clock Input; high impedance CMOS input used to clock serial data into registers with data latched on rising edge."+ "description": "Serial clock input for shifting 32-bit data words into the input shift register on rising clock edges." }, { "number": "15", "name": "DATA", "type": "input",- "description": "Serial Data Input; high impedance CMOS input, loaded MSB first with three LSBs as control bits."+ "description": "Serial data input receiving MSB-first data with control bits in three LSBs at high impedance." }, { "number": "16", "name": "LE", "type": "input",- "description": "Load Enable Input; high impedance CMOS input; when high, transfers data from shift register to selected latch."+ "description": "Load enable input that latches 32-bit word from shift register into target register on rising edge." }, { "number": "17", "name": "MUXOUT", "type": "tri_state",- "description": "Multiplexer Output; three-state output allowing access to various internal signals."+ "description": "Three-state multiplexer output providing access to internal signals including lock detect, divider outputs, and frequency readback." }, { "number": "18", "name": "SDVDD", "type": "power_in",- "description": "Power Supply for the Digital Σ-Δ Modulator (1.8 V); place decoupling capacitors to ground as close as possible."+ "description": "Positive 1.8 V power supply for \u03a3-\u0394 modulator with decoupling capacitors required close to pin." }, { "number": "19", "name": "DVDD", "type": "power_in",- "description": "Positive Power Supply for the Digital Section (1.8 V); place decoupling capacitors to ground as close as possible."+ "description": "Positive 1.62 to 1.98 V digital power supply for logic circuits with decoupling capacitors required close to pin." }, { "number": "20", "name": "SW1",- "type": "output",- "description": "Switch for Fast Lock; shorted to ground internally during fast lock operation for charge pump current boost."+ "type": "passive",+ "description": "Fast lock mode switch pin that is shorted to ground to modify loop filter resistance during wideband lock operation." }, { "number": "21", "name": "SW2",- "type": "output",- "description": "Switch for Fast Lock; connected to charge pump output internally during fast lock operation."+ "type": "passive",+ "description": "Fast lock mode switch pin that is connected to charge pump output for loop stabilization during wideband lock operation." }, { "number": "22", "name": "VP", "type": "power_in",- "description": "Charge Pump Power Supply (2.7-3.45 V); must be ≥ AVDD."+ "description": "Charge pump power supply accepting 2.7 to 3.45 V with requirement that VP \u2265 AVDD." }, { "number": "23", "name": "RSET", "type": "passive",- "description": "Charge Pump Current Setting; connect resistor to ground (4.59-5.61 kΩ) with ICP_MAX = 24.48/RSET."+ "description": "External resistor connection to ground for setting maximum charge pump current per ICP_MAX = 24.48 mA / RSET(k\u03a9)." }, { "number": "24", "name": "CP", "type": "output",- "description": "Charge Pump Output; when enabled provides ±ICP to external loop filter driving the VCO."+ "description": "Charge pump output providing \u00b10.31 to 5.0 mA programmable current to external loop filter and VCO." }, { "number": "25",- "name": "EP",- "type": "passive",- "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ "name": "EPAD",+ "type": "power_in",+ "description": "Exposed thermal and electrical ground pad that must be soldered to AGND for proper heat dissipation." } ], "provenance": {@@ -193,13 +193,10 @@ "consensus_model": "claude-sonnet-4-6", "consensus": "agreed", "guards": "pin_guards 0.1: passed",- "guard_notes": [- "exposed pad 25 added from the footprint",- "dropped thermal pad ['EP'] absent from footprint"- ],+ "guard_notes": [], "pages_sent": 36,- "cost_usd": 0.3453,- "at": "2026-09-17T17:31:59"+ "cost_usd": 0.3026,+ "at": "2026-09-17T17:54:06" }, "datasheet": { "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893849548689408",@@ -261,8 +258,5 @@ "docs/adf4159ccpz-rl7-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": {- "public": true- }+ ] }