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ADF4002BCPZ-RL7
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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# ADF4002BCPZ-RL7++**Analog Devices** · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-20(4x4)++ADF4002BCPZ-RL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPGND | power_in | Charge pump ground return path. |+| 2 | AGND | power_in | Analog ground return path for RF input stage. |+| 3 | AGND | power_in | Analog ground return path for RF input stage. |+| 4 | RFINB | input | Complementary RF input; must be decoupled to ground plane with 100 pF bypass capacitor. |+| 5 | RFINA | input | RF input signal ac-coupled to external VCO; frequency 5 to 400 MHz; input sensitivity −10 to 0 dBm. |+| 6 | AVDD | power_in | Analog power supply, 2.7 to 3.3 V; must equal DVDD. |+| 7 | AVDD | power_in | Analog power supply, 2.7 to 3.3 V; must equal DVDD. |+| 8 | REFIN | input | Reference clock input, CMOS with nominal threshold VDD/2; frequency 20 to 300 MHz; can be driven from TTL/CMOS crystal or ac-coupled. |+| 9 | DGND | power_in | Digital ground return path. |+| 10 | DGND | power_in | Digital ground return path. |+| 11 | CE | input | Chip enable input; logic low powers down device and puts charge pump into three-state mode. |+| 12 | CLK | input | Serial clock input; high impedance CMOS; data latched on rising edge at maximum rate 20 MHz. |+| 13 | DATA | input | Serial data input, high impedance CMOS; loaded MSB first with two LSBs as control bits. |+| 14 | LE | input | Load enable CMOS input; transfers data from shift registers to selected latch on high pulse; minimum pulse width 20 ns. |+| 15 | MUXOUT | output | Multiplexer output; selectable for lock detect, R counter, N counter, or internal signals via M3-M1 control bits. |+| 16 | DVDD | power_in | Digital power supply, 2.7 to 3.3 V; must equal AVDD. |+| 17 | DVDD | power_in | Digital power supply, 2.7 to 3.3 V; must equal AVDD. |+| 18 | VP | power_in | Charge pump power supply, AVDD to 5.5 V; allows VCO tuning range to 5 V in 3 V systems. |+| 19 | RSET | passive | External resistor to CPGND sets charge pump current per relationship ICP (mA) = 25.5 / RSET; range 3.0 to 11 kΩ; nominal voltage 0.66 V. |+| 20 | CP | output | Charge pump output; provides ±ICP (625 µA to 5 mA) to external loop filter when enabled; supports three-state mode. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-20(4x4) |+| Category | Clock/Timing |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `ADF4002BCPZ-RL7`+- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`+- 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)+- 3D model files: `adf4002bcpz-rl7-etched.step` / `adf4002bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adf4002bcpz-rl7.step` / `adf4002bcpz-rl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590147067340488704) (20 pp, sha256 `fc5279ef463a7fa2`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adf4002bcpz-rl7-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "adf4002bcpz-rl7",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adf4002bcpz-rl7.kicad_sym",+ "adf4002bcpz-rl7.kicad_mod",+ "adf4002bcpz-rl7.glb",+ "adf4002bcpz-rl7.step",+ "adf4002bcpz-rl7.lbr",+ "docs/hero.png",+ "docs/adf4002bcpz-rl7-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADF4002BCPZ-RL7",+ "manufacturer": "Analog Devices",+ "package": "LFCSP-20(4x4)",+ "pin_count": 21,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590147067340488704",+ "parts": {+ "symbol": "adf4002bcpz-rl7.kicad_sym",+ "footprint": "adf4002bcpz-rl7.kicad_mod",+ "model_3d": "adf4002bcpz-rl7-etched.glb",+ "model_3d_plain": "adf4002bcpz-rl7.glb",+ "model_3d_step": "adf4002bcpz-rl7-etched.step",+ "model_3d_step_plain": "adf4002bcpz-rl7.step",+ "lbr": "adf4002bcpz-rl7.lbr"+ },+ "distributor_links": {+ "lcsc": "C578975"+ },+ "pins": [+ {+ "number": "1",+ "name": "CPGND",+ "type": "power_in",+ "description": "Charge pump ground return path."+ },+ {+ "number": "2",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return path for RF input stage."+ },+ {+ "number": "3",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return path for RF input stage."+ },+ {+ "number": "4",+ "name": "RFINB",+ "type": "input",+ "description": "Complementary RF input; must be decoupled to ground plane with 100 pF bypass capacitor."+ },+ {+ "number": "5",+ "name": "RFINA",+ "type": "input",+ "description": "RF input signal ac-coupled to external VCO; frequency 5 to 400 MHz; input sensitivity −10 to 0 dBm."+ },+ {+ "number": "6",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 2.7 to 3.3 V; must equal DVDD."+ },+ {+ "number": "7",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 2.7 to 3.3 V; must equal DVDD."+ },+ {+ "number": "8",+ "name": "REFIN",+ "type": "input",+ "description": "Reference clock input, CMOS with nominal threshold VDD/2; frequency 20 to 300 MHz; can be driven from TTL/CMOS crystal or ac-coupled."+ },+ {+ "number": "9",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return path."+ },+ {+ "number": "10",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return path."+ },+ {+ "number": "11",+ "name": "CE",+ "type": "input",+ "description": "Chip enable input; logic low powers down device and puts charge pump into three-state mode."+ },+ {+ "number": "12",+ "name": "CLK",+ "type": "input",+ "description": "Serial clock input; high impedance CMOS; data latched on rising edge at maximum rate 20 MHz."+ },+ {+ "number": "13",+ "name": "DATA",+ "type": "input",+ "description": "Serial data input, high impedance CMOS; loaded MSB first with two LSBs as control bits."+ },+ {+ "number": "14",+ "name": "LE",+ "type": "input",+ "description": "Load enable CMOS input; transfers data from shift registers to selected latch on high pulse; minimum pulse width 20 ns."+ },+ {+ "number": "15",+ "name": "MUXOUT",+ "type": "output",+ "description": "Multiplexer output; selectable for lock detect, R counter, N counter, or internal signals via M3-M1 control bits."+ },+ {+ "number": "16",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply, 2.7 to 3.3 V; must equal AVDD."+ },+ {+ "number": "17",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply, 2.7 to 3.3 V; must equal AVDD."+ },+ {+ "number": "18",+ "name": "VP",+ "type": "power_in",+ "description": "Charge pump power supply, AVDD to 5.5 V; allows VCO tuning range to 5 V in 3 V systems."+ },+ {+ "number": "19",+ "name": "RSET",+ "type": "passive",+ "description": "External resistor to CPGND sets charge pump current per relationship ICP (mA) = 25.5 / RSET; range 3.0 to 11 kΩ; nominal voltage 0.66 V."+ },+ {+ "number": "20",+ "name": "CP",+ "type": "output",+ "description": "Charge pump output; provides ±ICP (625 µA to 5 mA) to external loop filter when enabled; supports three-state mode."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Exposed thermal pad (EP) documented in Figure 25 and Table 5; must be connected to AGND per datashee",+ "exposed pad 21 added from the footprint"+ ],+ "pages_sent": 20,+ "cost_usd": 0.2964,+ "at": "2026-09-21T17:28:00"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590147067340488704",+ "pages": 20,+ "sha256": "fc5279ef463a7fa2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}