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ADC78H89CIMT
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Texas Instruments Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# ADC78H89CIMT++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-16++ADC78H89CIMT from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CS | input | Chip select: a conversion begins on the falling edge of CS and continues as long as CS is held low. |+| 2 | NC | unconnected | Not connected internally; this pin can be left floating or tied to ground. |+| 3 | AVDD | power_in | Positive analog supply, +2.7V to +5.25V, to be bypassed to GND with 0.1 µF ceramic and 1 µF tantalum capacitors within 1 cm of the pin. |+| 4 | GND | power_in | Ground return for both analog and digital supplies; tied internally to pin 12 and must be held at the same potential. |+| 5 | AIN1 | input | Analog input, which can range from 0V to AVDD. |+| 6 | AIN2 | input | Analog input, which can range from 0V to AVDD. |+| 7 | AIN3 | input | Analog input, which can range from 0V to AVDD. |+| 8 | AIN4 | input | Analog input, which can range from 0V to AVDD. |+| 9 | AIN5 | input | Analog input, which can range from 0V to AVDD. |+| 10 | AIN6 | input | Analog input, which can range from 0V to AVDD. |+| 11 | AIN7 | input | Analog input, which can range from 0V to AVDD. |+| 12 | GND | power_in | Ground return for both analog and digital supplies; tied internally to pin 4 and must be held at the same potential. |+| 13 | DVDD | power_in | Positive digital supply, +2.7V to AVDD, to be bypassed to GND with a 0.1 µF ceramic capacitor within 1 cm of the pin. |+| 14 | DIN | input | Digital data input; the Control Register is loaded through this pin on rising edges of SCLK. |+| 15 | DOUT | output | Digital data output; output samples are clocked out on falling edges of SCLK. |+| 16 | SCLK | input | Digital clock input, 50 kHz to 8 MHz with ensured performance at 8 MHz, which directly controls conversion and readout. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `ADC78H89CIMT`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `adc78h89cimt-etched.step` / `adc78h89cimt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc78h89cimt.step` / `adc78h89cimt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc78h89) (26 pp, sha256 `1086ead50d53818b`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc78h89cimt-datasheet.pdf)
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this pin can be left floating or tied to ground."+ },+ {+ "number": "3",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive analog supply, +2.7V to +5.25V, to be bypassed to GND with 0.1 µF ceramic and 1 µF tantalum capacitors within 1 cm of the pin."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for both analog and digital supplies; tied internally to pin 12 and must be held at the same potential."+ },+ {+ "number": "5",+ "name": "AIN1",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "6",+ "name": "AIN2",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "7",+ "name": "AIN3",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "8",+ "name": "AIN4",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "9",+ "name": "AIN5",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "10",+ "name": "AIN6",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "11",+ "name": "AIN7",+ "type": "input",+ "description": "Analog input, which can range from 0V to AVDD."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for both analog and digital supplies; tied internally to pin 4 and must be held at the same potential."+ },+ {+ "number": "13",+ "name": "DVDD",+ "type": "power_in",+ "description": "Positive digital supply, +2.7V to AVDD, to be bypassed to GND with a 0.1 µF ceramic capacitor within 1 cm of the pin."+ },+ {+ "number": "14",+ "name": "DIN",+ "type": "input",+ "description": "Digital data input; the Control Register is loaded through this pin on rising edges of SCLK."+ },+ {+ "number": "15",+ "name": "DOUT",+ "type": "output",+ "description": "Digital data output; output samples are clocked out on falling edges of SCLK."+ },+ {+ "number": "16",+ "name": "SCLK",+ "type": "input",+ "description": "Digital clock input, 50 kHz to 8 MHz with ensured performance at 8 MHz, which directly controls conversion and readout."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin table gives AIN1 to AIN7 as a single range on pins 5-11 without listing each pin i; Pin numbers are from the pin description table on page 2 and the 16-lead TSSOP connection diagram on"+ ],+ "pages_sent": 6,+ "cost_usd": 0.0475,+ "at": "2026-10-08T04:17:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/adc78h89",+ "pages": 26,+ "sha256": "1086ead50d53818b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adc78h89cimt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adc78h89cimt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9f5b98ad1b22dffef1398b473470d8871f722a9139f025cd643d04be56d49bf0",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}