component
ADC122S051QIMM
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Texas Instruments Analog To Digital Converters (ADCs), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# ADC122S051QIMM++**Texas Instruments** · Analog To Digital Converters (ADCs) · VSSOP-8++ADC122S051QIMM from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CS | input | Chip select: a falling edge on CS starts a conversion, and conversions continue as long as CS is held low. |+| 2 | VA | power_in | Positive supply, to be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. |+| 3 | GND | power_in | Ground return for the die. |+| 4 | IN2 | input | Analog input channel 2, which can range from 0V to VA. |+| 5 | IN1 | input | Analog input channel 1, which can range from 0V to VA. |+| 6 | DIN | input | Digital data input through which the Control Register is loaded on rising edges of SCLK; digital input voltage range is −0.3V to VA. |+| 7 | DOUT | output | Digital data output, with samples clocked out on falling edges of the SCLK pin. |+| 8 | SCLK | input | Digital clock input that directly controls the conversion and readout processes; clock frequency range is 50 kHz to 16 MHz. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-8 |+| Category | ADC/DAC/Data Conversion |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `ADC122S051QIMM`+- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`+- 3D model: VSSOP-8 (KiCad packages3D, STEP)+- 3D model files: `adc122s051qimm-etched.step` / `adc122s051qimm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc122s051qimm.step` / `adc122s051qimm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc122s051q-q1) (29 pp, sha256 `c0d986b74f1142a3`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc122s051qimm-datasheet.pdf)
page.jsonadded+197@@ -0,0 +1,197 @@+{+ "slug": "adc122s051qimm",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADCs), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "adc122s051qimm",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adc122s051qimm.kicad_sym",+ "adc122s051qimm.kicad_mod",+ "adc122s051qimm.glb",+ "adc122s051qimm.step",+ "adc122s051qimm.lbr",+ "docs/hero.png",+ "docs/adc122s051qimm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "adc122s051qimm-hero.glb",+ "adc122s051qimm-hero.overlay.json"+ ],+ "component": {+ "mpn": "ADC122S051QIMM",+ "manufacturer": "Texas Instruments",+ "package": "VSSOP-8",+ "pin_count": 8,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Analog To Digital Converters (ADCs)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/adc122s051q-q1",+ "parts": {+ "symbol": "adc122s051qimm.kicad_sym",+ "footprint": "adc122s051qimm.kicad_mod",+ "model_3d": "adc122s051qimm-hero.glb",+ "model_3d_plain": "adc122s051qimm.glb",+ "model_3d_step": "adc122s051qimm-etched.step",+ "model_3d_step_plain": "adc122s051qimm.step",+ "lbr": "adc122s051qimm.lbr"+ },+ "distributor_links": {+ "lcsc": "C2670344"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T03:01:08Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CS",+ "type": "input",+ "description": "Chip select: a falling edge on CS starts a conversion, and conversions continue as long as CS is held low."+ },+ {+ "number": "2",+ "name": "VA",+ "type": "power_in",+ "description": "Positive supply, to be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for the die."+ },+ {+ "number": "4",+ "name": "IN2",+ "type": "input",+ "description": "Analog input channel 2, which can range from 0V to VA."+ },+ {+ "number": "5",+ "name": "IN1",+ "type": "input",+ "description": "Analog input channel 1, which can range from 0V to VA."+ },+ {+ "number": "6",+ "name": "DIN",+ "type": "input",+ "description": "Digital data input through which the Control Register is loaded on rising edges of SCLK; digital input voltage range is −0.3V to VA."+ },+ {+ "number": "7",+ "name": "DOUT",+ "type": "output",+ "description": "Digital data output, with samples clocked out on falling edges of the SCLK pin."+ },+ {+ "number": "8",+ "name": "SCLK",+ "type": "input",+ "description": "Digital clock input that directly controls the conversion and readout processes; clock frequency range is 50 kHz to 16 MHz."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin table lists '5,4 IN1 and IN2' without an explicit per-pin mapping. IN1 is assigned; The package is confirmed as 8-lead VSSOP (DGK) by the datasheet text and the package option addendum"+ ],+ "pages_sent": 6,+ "cost_usd": 0.0427,+ "at": "2026-10-08T03:00:52"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/adc122s051q-q1",+ "pages": 29,+ "sha256": "c0d986b74f1142a3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adc122s051qimm.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.1,+ 2,+ 0.85+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adc122s051qimm-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.1,+ 2,+ 0.85+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8ba8179e0ad00d292132cc5dd6ace88b871c1e0a372141ae8f88fd5fea838766",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}