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Initial commit: component/adc1173cimtcx

Ray ·ebf9a709bf ·3d ago
2 files changed +316
README.mdadded+60
@@ -0,0 +1,60 @@+# ADC1173CIMTCX++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-24++ADC1173CIMTCX from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | CMOS/TTL compatible digital input that enables the digital outputs when low and places them in high impedance state when high. |+| 2 | DVSS | power_in | Ground return for the digital supply. |+| 3 | D0 | tri_state | Conversion data digital output pin (LSB), valid just after rising edge of CLK input, enabled by OE low. |+| 4 | D1 | tri_state | Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low. |+| 5 | D2 | tri_state | Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low. |+| 6 | D3 | tri_state | Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low. |+| 7 | D4 | tri_state | Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low. |+| 8 | D5 | tri_state | Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low. |+| 9 | D6 | tri_state | Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low. |+| 10 | D7 | tri_state | Conversion data digital output pin (MSB), valid just after rising edge of CLK input, enabled by OE low. |+| 11 | DVDD | power_in | Positive digital supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors. |+| 12 | CLK | input | CMOS/TTL compatible digital clock input, VIN sampled on falling edge of CLK. |+| 13 | DVDD | power_in | Positive digital supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors. |+| 14 | AVDD | power_in | Positive analog supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors. |+| 15 | AVDD | power_in | Positive analog supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors. |+| 16 | VRTS | input | Reference Top Bias with internal pull-up resistor, short to VRT to self bias the reference ladder. |+| 17 | VRT | input | Analog input for high side of reference ladder, nominal range 1.0V to AVDD, bypass well. |+| 18 | AVDD | power_in | Positive analog supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors. |+| 19 | VIN | power_in | Analog signal input, conversion range is VRB to VRT. |+| 20 | AVSS | power_in | Ground return for the analog supply, connect close to ADC1173 package. |+| 21 | AVSS | power_in | Ground return for the analog supply, connect close to ADC1173 package. |+| 22 | VRBS | input | Reference Bottom Bias with internal pull down resistor, short to VRB to self bias the reference ladder. |+| 23 | VRB | input | Analog input for low side of reference ladder, nominal range 0V to 2.0V, bypass well. |+| 24 | DVSS | power_in | Ground return for the digital supply. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Data Acquisition |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `ADC1173CIMTCX`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `adc1173cimtcx-etched.step` / `adc1173cimtcx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc1173cimtcx.step` / `adc1173cimtcx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc1173) (32 pp, sha256 `d082ff2da3517ea6`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc1173cimtcx-datasheet.pdf)
page.jsonadded+256
@@ -0,0 +1,256 @@+{+  "slug": "adc1173cimtcx",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "adc1173cimtcx",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "adc1173cimtcx.kicad_sym",+    "adc1173cimtcx.kicad_mod",+    "adc1173cimtcx.glb",+    "adc1173cimtcx.step",+    "adc1173cimtcx.lbr",+    "docs/hero.png",+    "docs/adc1173cimtcx-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "adc1173cimtcx-hero.glb",+    "adc1173cimtcx-hero.overlay.json"+  ],+  "component": {+    "mpn": "ADC1173CIMTCX",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-24",+    "pin_count": 24,+    "category": "Data Acquisition",+    "subcategory": "Analog To Digital Converters (ADC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/adc1173",+    "parts": {+      "symbol": "adc1173cimtcx.kicad_sym",+      "footprint": "adc1173cimtcx.kicad_mod",+      "model_3d": "adc1173cimtcx-hero.glb",+      "model_3d_plain": "adc1173cimtcx.glb",+      "model_3d_step": "adc1173cimtcx-etched.step",+      "model_3d_step_plain": "adc1173cimtcx.step",+      "lbr": "adc1173cimtcx.lbr"+    },+    "distributor_links": {+      "lcsc": 701593,+      "mouser": "926-ADC1173CIMTCX"+    },+    "distributor_check": {+      "checked_at": "2026-10-03T04:51:34Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": null,+        "status": "no match"+      },+      "mouser": {+        "pn": "926-ADC1173CIMTCX",+        "status": "found",+        "lifecycle": "Obsolete"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "OE",+        "type": "input",+        "description": "CMOS/TTL compatible digital input that enables the digital outputs when low and places them in high impedance state when high."+      },+      {+        "number": "2",+        "name": "DVSS",+        "type": "power_in",+        "description": "Ground return for the digital supply."+      },+      {+        "number": "3",+        "name": "D0",+        "type": "tri_state",+        "description": "Conversion data digital output pin (LSB), valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "4",+        "name": "D1",+        "type": "tri_state",+        "description": "Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "5",+        "name": "D2",+        "type": "tri_state",+        "description": "Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "6",+        "name": "D3",+        "type": "tri_state",+        "description": "Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "7",+        "name": "D4",+        "type": "tri_state",+        "description": "Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "8",+        "name": "D5",+        "type": "tri_state",+        "description": "Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "9",+        "name": "D6",+        "type": "tri_state",+        "description": "Conversion data digital output pin, valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "10",+        "name": "D7",+        "type": "tri_state",+        "description": "Conversion data digital output pin (MSB), valid just after rising edge of CLK input, enabled by OE low."+      },+      {+        "number": "11",+        "name": "DVDD",+        "type": "power_in",+        "description": "Positive digital supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors."+      },+      {+        "number": "12",+        "name": "CLK",+        "type": "input",+        "description": "CMOS/TTL compatible digital clock input, VIN sampled on falling edge of CLK."+      },+      {+        "number": "13",+        "name": "DVDD",+        "type": "power_in",+        "description": "Positive digital supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors."+      },+      {+        "number": "14",+        "name": "AVDD",+        "type": "power_in",+        "description": "Positive analog supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors."+      },+      {+        "number": "15",+        "name": "AVDD",+        "type": "power_in",+        "description": "Positive analog supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors."+      },+      {+        "number": "16",+        "name": "VRTS",+        "type": "input",+        "description": "Reference Top Bias with internal pull-up resistor, short to VRT to self bias the reference ladder."+      },+      {+        "number": "17",+        "name": "VRT",+        "type": "input",+        "description": "Analog input for high side of reference ladder, nominal range 1.0V to AVDD, bypass well."+      },+      {+        "number": "18",+        "name": "AVDD",+        "type": "power_in",+        "description": "Positive analog supply pin, connect to +3V source, bypass with 10µF and 0.1µF ceramic capacitors."+      },+      {+        "number": "19",+        "name": "VIN",+        "type": "power_in",+        "description": "Analog signal input, conversion range is VRB to VRT."+      },+      {+        "number": "20",+        "name": "AVSS",+        "type": "power_in",+        "description": "Ground return for the analog supply, connect close to ADC1173 package."+      },+      {+        "number": "21",+        "name": "AVSS",+        "type": "power_in",+        "description": "Ground return for the analog supply, connect close to ADC1173 package."+      },+      {+        "number": "22",+        "name": "VRBS",+        "type": "input",+        "description": "Reference Bottom Bias with internal pull down resistor, short to VRB to self bias the reference ladder."+      },+      {+        "number": "23",+        "name": "VRB",+        "type": "input",+        "description": "Analog input for low side of reference ladder, nominal range 0V to 2.0V, bypass well."+      },+      {+        "number": "24",+        "name": "DVSS",+        "type": "power_in",+        "description": "Ground return for the digital supply."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "3/24 pins cited to the wrong page (name found elsewhere): ['5:D2@p4', '8:D5@p4', '9:D6@p4']",+          "1/24 pin names appear NOWHERE in the datasheet text: ['7:D4@p4']"+        ],+        "pages_sent": 8,+        "cost_usd": 0.1134,+        "at": "2026-10-03T04:51:07"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/adc1173",+        "pages": 32,+        "sha256": "d082ff2da3517ea6",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 24,+        "described": 24,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file