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ADC08100CIMTCX
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Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# ADC08100CIMTCX++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-24++ADC08100CIMTCX from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VA | power_in | Positive analog supply pin (+3V) requiring bypass of 0.1 µF ceramic chip capacitor per pin plus one 10 µF capacitor. |+| 2 | AGND | power_in | Ground return for the analog supply. |+| 3 | VRT | input | Analog input for the high (top) side of the reference ladder with nominal range 1.0V to VA, defining VIN conversion range with VRB. |+| 4 | VA | power_in | Positive analog supply pin (+3V) requiring bypass of 0.1 µF ceramic chip capacitor per pin plus one 10 µF capacitor. |+| 5 | AGND | power_in | Ground return for the analog supply. |+| 6 | VIN | power_in | Analog signal input with conversion range from VRB to VRT. |+| 7 | VIN GND | power_in | Reference ground for the single-ended analog input VIN. |+| 8 | AGND | power_in | Ground return for the analog supply. |+| 9 | VRM | input | Mid-point of the reference ladder requiring bypass capacitor of 0.1 µF to the analog ground plane. |+| 10 | VRB | input | Analog input for the low (bottom) side of the reference ladder with nominal range 0.0V to (VRT - 1.0V), defining VIN conversion range with VRT. |+| 11 | AGND | power_in | Ground return for the analog supply. |+| 12 | VA | power_in | Positive analog supply pin (+3V) requiring bypass of 0.1 µF ceramic chip capacitor per pin plus one 10 µF capacitor. |+| 13 | D0 | output | Conversion data digital output pin (LSB) with valid data output just after the rising edge of CLK input. |+| 14 | D1 | output | Conversion data digital output pin with valid data output just after the rising edge of CLK input. |+| 15 | D2 | output | Conversion data digital output pin with valid data output just after the rising edge of CLK input. |+| 16 | D3 | output | Conversion data digital output pin with valid data output just after the rising edge of CLK input. |+| 17 | DR GND | power_in | Ground return for the output driver supply. |+| 18 | DR VD | power_in | Power supply for the output drivers requiring decoupling from VA when connected. |+| 19 | D4 | output | Conversion data digital output pin with valid data output just after the rising edge of CLK input. |+| 20 | D5 | output | Conversion data digital output pin with valid data output just after the rising edge of CLK input. |+| 21 | D6 | output | Conversion data digital output pin with valid data output just after the rising edge of CLK input. |+| 22 | D7 | output | Conversion data digital output pin (MSB) with valid data output just after the rising edge of CLK input. |+| 23 | PD | input | Power Down input that when high places converter in Power Down mode with data output pins holding the last conversion result. |+| 24 | CLK | input | CMOS/TTL compatible digital clock input where VIN is sampled on the falling edge. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Data Acquisition |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `ADC08100CIMTCX`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `adc08100cimtcx-etched.step` / `adc08100cimtcx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc08100cimtcx.step` / `adc08100cimtcx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc08100) (30 pp, sha256 `b8771ba4144fdf8c`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc08100cimtcx-datasheet.pdf)
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1.0V), defining VIN conversion range with VRT."+ },+ {+ "number": "11",+ "name": "AGND",+ "type": "power_in",+ "description": "Ground return for the analog supply."+ },+ {+ "number": "12",+ "name": "VA",+ "type": "power_in",+ "description": "Positive analog supply pin (+3V) requiring bypass of 0.1 µF ceramic chip capacitor per pin plus one 10 µF capacitor."+ },+ {+ "number": "13",+ "name": "D0",+ "type": "output",+ "description": "Conversion data digital output pin (LSB) with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "14",+ "name": "D1",+ "type": "output",+ "description": "Conversion data digital output pin with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "15",+ "name": "D2",+ "type": "output",+ "description": "Conversion data digital output pin with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "16",+ "name": "D3",+ "type": "output",+ "description": "Conversion data digital output pin with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "17",+ "name": "DR GND",+ "type": "power_in",+ "description": "Ground return for the output driver supply."+ },+ {+ "number": "18",+ "name": "DR VD",+ "type": "power_in",+ "description": "Power supply for the output drivers requiring decoupling from VA when connected."+ },+ {+ "number": "19",+ "name": "D4",+ "type": "output",+ "description": "Conversion data digital output pin with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "20",+ "name": "D5",+ "type": "output",+ "description": "Conversion data digital output pin with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "21",+ "name": "D6",+ "type": "output",+ "description": "Conversion data digital output pin with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "22",+ "name": "D7",+ "type": "output",+ "description": "Conversion data digital output pin (MSB) with valid data output just after the rising edge of CLK input."+ },+ {+ "number": "23",+ "name": "PD",+ "type": "input",+ "description": "Power Down input that when high places converter in Power Down mode with data output pins holding the last conversion result."+ },+ {+ "number": "24",+ "name": "CLK",+ "type": "input",+ "description": "CMOS/TTL compatible digital clock input where VIN is sampled on the falling edge."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "4/24 pins cited to the wrong page (name found elsewhere): ['14:D1@p3', '15:D2@p3', '20:D5@p3', '21:D6@p3']"+ ],+ "pages_sent": 7,+ "cost_usd": 0.0947,+ "at": "2026-10-07T08:50:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/adc08100",+ "pages": 30,+ "sha256": "b8771ba4144fdf8c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adc08100cimtcx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adc08100cimtcx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a858b16629db63d40231d8a7a518da1afdc28ff030e34a7a47e5cf5bd3d9c2ac",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}