component
AD9910BSVZ-REEL
Public Made by Adomby adom
Analog Devices Direct Digital Synthesis (DDS), TQFP-100-EP(14x14). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+680−8@@ -1,13 +1,690 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ad9910bsvz-reel",+ "title": "AD9910BSVZ-REEL",+ "brief": "Analog Devices Direct Digital Synthesis (DDS), TQFP-100-EP(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Analog Devices Direct Digital Synthesis (DDS), TQFP-100-EP(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "data acquisition", "ad9910bsvz-reel" ],+ "component": {+ "mpn": "AD9910BSVZ-REEL",+ "manufacturer": "Analog Devices",+ "package": "TQFP-100-EP(14x14)",+ "pin_count": 101,+ "category": "Data Acquisition",+ "subcategory": "Direct Digital Synthesis (DDS)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589839071616278528",+ "parts": {+ "symbol": "ad9910bsvz-reel.kicad_sym",+ "footprint": "ad9910bsvz-reel.kicad_mod",+ "model_3d": "ad9910bsvz-reel.glb",+ "model_3d_step": "ad9910bsvz-reel.step",+ "lbr": "ad9910bsvz-reel.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "2",+ "name": "PLL_LOOP_FILTER",+ "type": "passive",+ "description": "PLL Loop Filter Compensation Pin. External RC network sets loop dynamics of the REFCLK multiplier PLL."+ },+ {+ "number": "3",+ "name": "AVDD_1V8",+ "type": "power_in",+ "description": "Analog Core VDD, 1.8 V analog supply."+ },+ {+ "number": "4",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "5",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "6",+ "name": "AVDD_1V8",+ "type": "power_in",+ "description": "Analog Core VDD, 1.8 V analog supply."+ },+ {+ "number": "7",+ "name": "SYNC_IN+",+ "type": "input",+ "description": "LVDS synchronization signal input (rising edge active). Positive leg of differential sync input from an external master to synchronize internal subclocks."+ },+ {+ "number": "8",+ "name": "SYNC_IN-",+ "type": "input",+ "description": "LVDS synchronization signal input. Negative leg of differential sync input from an external master to synchronize internal subclocks."+ },+ {+ "number": "9",+ "name": "SYNC_OUT+",+ "type": "output",+ "description": "LVDS synchronization signal output (rising edge active). Positive leg of differential sync output used to synchronize external slave devices."+ },+ {+ "number": "10",+ "name": "SYNC_OUT-",+ "type": "output",+ "description": "LVDS synchronization signal output. Negative leg of differential sync output used to synchronize external slave devices."+ },+ {+ "number": "11",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "12",+ "name": "SYNC_SMP_ERR",+ "type": "output",+ "description": "Synchronization Sample Error, digital output (active high). A high indicates the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN-."+ },+ {+ "number": "13",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "14",+ "name": "MASTER_RESET",+ "type": "input",+ "description": "Master Reset, digital input (active high). Clears all memory elements and sets registers to default values."+ },+ {+ "number": "15",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "16",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "17",+ "name": "DVDD_1V8",+ "type": "power_in",+ "description": "Digital Core VDD, 1.8 V digital supply."+ },+ {+ "number": "18",+ "name": "EXT_PWR_DWN",+ "type": "input",+ "description": "External Power-Down, digital input (active high). Initiates the currently programmed power-down mode. Tie to ground if unused."+ },+ {+ "number": "19",+ "name": "PLL_LOCK",+ "type": "output",+ "description": "Clock Multiplier PLL Lock, digital output (active high). A high indicates the REFCLK multiplier PLL has acquired lock."+ },+ {+ "number": "20",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "21",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "22",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "23",+ "name": "DVDD_1V8",+ "type": "power_in",+ "description": "Digital Core VDD, 1.8 V digital supply."+ },+ {+ "number": "24",+ "name": "RAM_SWP_OVR",+ "type": "output",+ "description": "RAM Sweep Over, digital output (active high). A high indicates that the RAM sweep profile has completed."+ },+ {+ "number": "25",+ "name": "D15",+ "type": "input",+ "description": "Parallel Input Bus bit 15 (active high). Modulation data for the parallel data port."+ },+ {+ "number": "26",+ "name": "D14",+ "type": "input",+ "description": "Parallel Input Bus bit 14 (active high)."+ },+ {+ "number": "27",+ "name": "D13",+ "type": "input",+ "description": "Parallel Input Bus bit 13 (active high)."+ },+ {+ "number": "28",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "29",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "30",+ "name": "DVDD_1V8",+ "type": "power_in",+ "description": "Digital Core VDD, 1.8 V digital supply."+ },+ {+ "number": "31",+ "name": "D12",+ "type": "input",+ "description": "Parallel Input Bus bit 12 (active high)."+ },+ {+ "number": "32",+ "name": "D11",+ "type": "input",+ "description": "Parallel Input Bus bit 11 (active high)."+ },+ {+ "number": "33",+ "name": "D10",+ "type": "input",+ "description": "Parallel Input Bus bit 10 (active high)."+ },+ {+ "number": "34",+ "name": "D9",+ "type": "input",+ "description": "Parallel Input Bus bit 9 (active high)."+ },+ {+ "number": "35",+ "name": "D8",+ "type": "input",+ "description": "Parallel Input Bus bit 8 (active high)."+ },+ {+ "number": "36",+ "name": "D7",+ "type": "input",+ "description": "Parallel Input Bus bit 7 (active high)."+ },+ {+ "number": "37",+ "name": "D6",+ "type": "input",+ "description": "Parallel Input Bus bit 6 (active high)."+ },+ {+ "number": "38",+ "name": "D5",+ "type": "input",+ "description": "Parallel Input Bus bit 5 (active high)."+ },+ {+ "number": "39",+ "name": "D4",+ "type": "input",+ "description": "Parallel Input Bus bit 4 (active high)."+ },+ {+ "number": "40",+ "name": "PDCLK",+ "type": "output",+ "description": "Parallel Data Clock, digital output. Provides a timing signal for aligning data at the parallel inputs."+ },+ {+ "number": "41",+ "name": "TxENABLE",+ "type": "input",+ "description": "Transmit Enable, digital input (active high). In burst mode a high indicates new data for transmission; in continuous mode this pin remains high."+ },+ {+ "number": "42",+ "name": "D3",+ "type": "input",+ "description": "Parallel Input Bus bit 3 (active high)."+ },+ {+ "number": "43",+ "name": "D2",+ "type": "input",+ "description": "Parallel Input Bus bit 2 (active high)."+ },+ {+ "number": "44",+ "name": "D1",+ "type": "input",+ "description": "Parallel Input Bus bit 1 (active high)."+ },+ {+ "number": "45",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "46",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "47",+ "name": "DVDD_1V8",+ "type": "power_in",+ "description": "Digital Core VDD, 1.8 V digital supply."+ },+ {+ "number": "48",+ "name": "D0",+ "type": "input",+ "description": "Parallel Input Bus bit 0 (active high)."+ },+ {+ "number": "49",+ "name": "F1",+ "type": "input",+ "description": "Modulation Format Pin F[1]. Digital input that determines the parallel-port modulation format."+ },+ {+ "number": "50",+ "name": "F0",+ "type": "input",+ "description": "Modulation Format Pin F[0]. Digital input that determines the parallel-port modulation format."+ },+ {+ "number": "51",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "52",+ "name": "PROFILE2",+ "type": "input",+ "description": "Profile Select Pin bit 2 (active high). Selects one of eight phase/frequency profiles for the DDS."+ },+ {+ "number": "53",+ "name": "PROFILE1",+ "type": "input",+ "description": "Profile Select Pin bit 1 (active high). Selects one of eight phase/frequency profiles for the DDS."+ },+ {+ "number": "54",+ "name": "PROFILE0",+ "type": "input",+ "description": "Profile Select Pin bit 0 (active high). Selects one of eight phase/frequency profiles for the DDS."+ },+ {+ "number": "55",+ "name": "SYNC_CLK",+ "type": "output",+ "description": "Output Clock Divided-By-Four. Digital output clock; many digital inputs (I/O_UPDATE, PROFILE[2:0], etc.) must be set up on the rising edge of this signal."+ },+ {+ "number": "56",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "57",+ "name": "DVDD_1V8",+ "type": "power_in",+ "description": "Digital Core VDD, 1.8 V digital supply."+ },+ {+ "number": "58",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "59",+ "name": "I/O_UPDATE",+ "type": "bidirectional",+ "description": "Input/Output Update, digital I/O (active high). A high transfers the contents of the I/O buffers to the corresponding internal registers."+ },+ {+ "number": "60",+ "name": "OSK",+ "type": "input",+ "description": "Output Shift Keying, digital input (active high). Controls the OSK function; in manual mode toggles amplitude between zero and programmed scale, in automatic mode sweeps amplitude down/up."+ },+ {+ "number": "61",+ "name": "DROVER",+ "type": "output",+ "description": "Digital Ramp Over, digital output (active high). Switches high whenever the digital ramp generator reaches its programmed upper or lower limit."+ },+ {+ "number": "62",+ "name": "DRCTL",+ "type": "input",+ "description": "Digital Ramp Control, digital input (active high). Controls the slope polarity of the digital ramp generator. Tie low if DRG unused."+ },+ {+ "number": "63",+ "name": "DRHOLD",+ "type": "input",+ "description": "Digital Ramp Hold, digital input (active high). Stalls the digital ramp generator in its present state. Tie low if DRG unused."+ },+ {+ "number": "64",+ "name": "DVDD_1V8",+ "type": "power_in",+ "description": "Digital Core VDD, 1.8 V digital supply."+ },+ {+ "number": "65",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground."+ },+ {+ "number": "66",+ "name": "DVDD_IO_3V3",+ "type": "power_in",+ "description": "Digital Input/Output VDD, 3.3 V digital supply."+ },+ {+ "number": "67",+ "name": "SDIO",+ "type": "bidirectional",+ "description": "Serial Data Input/Output (active high). Bidirectional serial data line by default; unidirectional (input only) when configured."+ },+ {+ "number": "68",+ "name": "SDO",+ "type": "output",+ "description": "Serial Data Output, digital output (active high). Only active in unidirectional serial data mode; leave floating in bidirectional mode."+ },+ {+ "number": "69",+ "name": "SCLK",+ "type": "input",+ "description": "Serial Data Clock. Rising edge on write, falling edge on read. Provides the serial data clock for the control data path."+ },+ {+ "number": "70",+ "name": "CS",+ "type": "input",+ "description": "Chip Select, digital input (active low). Low enables the AD9910 to detect serial clock rising/falling edges on the serial data pins; high causes it to ignore input."+ },+ {+ "number": "71",+ "name": "I/O_RESET",+ "type": "input",+ "description": "Input/Output Reset, digital input (active high). Used when a serial I/O communication cycle fails. Tie to ground when not used."+ },+ {+ "number": "72",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "73",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "74",+ "name": "AVDD_3V3",+ "type": "power_in",+ "description": "Analog DAC VDD, 3.3 V analog supply."+ },+ {+ "number": "75",+ "name": "AVDD_3V3",+ "type": "power_in",+ "description": "Analog DAC VDD, 3.3 V analog supply."+ },+ {+ "number": "76",+ "name": "AVDD_3V3",+ "type": "power_in",+ "description": "Analog DAC VDD, 3.3 V analog supply."+ },+ {+ "number": "77",+ "name": "AVDD_3V3",+ "type": "power_in",+ "description": "Analog DAC VDD, 3.3 V analog supply."+ },+ {+ "number": "78",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "79",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "80",+ "name": "IOUTB",+ "type": "output",+ "description": "Open-Drain DAC Complementary Output Source, analog current-mode output. Connect through a 50 ohm resistor to AGND."+ },+ {+ "number": "81",+ "name": "IOUT",+ "type": "output",+ "description": "Open-Drain DAC Output Source, analog current-mode output. Connect through a 50 ohm resistor to AGND."+ },+ {+ "number": "82",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "83",+ "name": "AVDD_3V3",+ "type": "power_in",+ "description": "Analog DAC VDD, 3.3 V analog supply."+ },+ {+ "number": "84",+ "name": "DAC_RSET",+ "type": "passive",+ "description": "Analog Reference Pin. Programs the DAC output full-scale reference current. Attach a 10 kohm resistor to AGND."+ },+ {+ "number": "85",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "86",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "87",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "88",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "89",+ "name": "AVDD_1V8",+ "type": "power_in",+ "description": "Analog Core VDD, 1.8 V analog supply."+ },+ {+ "number": "90",+ "name": "REF_CLK",+ "type": "input",+ "description": "Reference Clock Input, analog input. Can be driven by an external oscillator or connected to a crystal when the internal oscillator is engaged."+ },+ {+ "number": "91",+ "name": "REF_CLKB",+ "type": "input",+ "description": "Reference Clock Input (complementary), analog input. Negative leg of the differential reference clock."+ },+ {+ "number": "92",+ "name": "AVDD_1V8",+ "type": "power_in",+ "description": "Analog Core VDD, 1.8 V analog supply."+ },+ {+ "number": "93",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "94",+ "name": "REFCLK_OUT",+ "type": "output",+ "description": "Crystal Output, analog output. Used with the internal oscillator when driven from a crystal (see REF_CLK Overview)."+ },+ {+ "number": "95",+ "name": "XTAL_SEL",+ "type": "input",+ "description": "Crystal Select (1.8 V logic), analog input (active high). Driving high enables the internal oscillator to be used with a crystal resonator. Tie to AGND if unused."+ },+ {+ "number": "96",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground."+ },+ {+ "number": "97",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "98",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "99",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "100",+ "name": "NC",+ "type": "unconnected",+ "description": "Not Connected. Allow device pin to float."+ },+ {+ "number": "EPAD",+ "name": "EPAD",+ "type": "power_in",+ "description": "Exposed Paddle. Must be soldered to ground for proper thermal and electrical performance."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589839071616278528",+ "pages": 64,+ "sha256": "e84adc31ccf0b2ff",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 101,+ "described": 101,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Analog Devices",+ "Package": "TQFP-100-EP(14x14)",+ "Category": "Data Acquisition",+ "Pins": "101"+ }+ },+ "variants": [+ {+ "mpn": "AD9910BSVZ-REEL",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ad9910bsvz-reel"+ ],+ "discovery_pitch": "AD9910BSVZ-REEL (Analog Devices) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +702,5 @@ "docs/ad9910bsvz-reel-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }