AD9753ASTZRL

@@ -0,0 +1,90 @@+# AD9753ASTZRL++**Analog Devices** · Digital To Analog Converters (DAC) · LQFP-48(7x7)++AD9753ASTZRL from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RESET | input | Internal clock divider reset (CMOS logic input, 0/3.3 V). |+| 2 | CLK+ | input | Differential clock input, positive leg. Can also be driven single-ended. Input range 0-3 V, differential swing 0.5-1.5 V, common-mode 0.75-2.25 V. Minimum 6.25 MHz when PLL is enabled. |+| 3 | CLK- | input | Differential clock input, negative leg. Complements CLK+ when driven differentially. |+| 4 | DCOM | power_in | Digital ground return for DVDD. |+| 5 | DVDD | power_in | Digital supply voltage, 3.0-3.6 V (3.3 V nom). Digital supply current I_DVDD ≈ 3.5 mA typ. |+| 6 | PLLLOCK | output | Phase-locked loop lock indicator output. CMOS output; V_OH ≥ 3.0 V, V_OL ≤ 0.3 V. |+| 7 | MSB-P1B11 | input | Port 1 parallel data input, bit DB11 (MSB). CMOS levels referenced to DVDD/DCOM. |+| 8 | P1B10 | input | Port 1 parallel data input, bit DB10. |+| 9 | P1B9 | input | Port 1 parallel data input, bit DB9. |+| 10 | P1B8 | input | Port 1 parallel data input, bit DB8. |+| 11 | P1B7 | input | Port 1 parallel data input, bit DB7. |+| 12 | P1B6 | input | Port 1 parallel data input, bit DB6. |+| 13 | P1B5 | input | Port 1 parallel data input, bit DB5. |+| 14 | P1B4 | input | Port 1 parallel data input, bit DB4. |+| 15 | P1B3 | input | Port 1 parallel data input, bit DB3. |+| 16 | P1B2 | input | Port 1 parallel data input, bit DB2. |+| 17 | P1B1 | input | Port 1 parallel data input, bit DB1. |+| 18 | LSB-P1B0 | input | Port 1 parallel data input, bit DB0 (LSB). |+| 19 | RESERVED | unconnected | Reserved - no user connection. Leave floating. |+| 20 | RESERVED | unconnected | Reserved - no user connection. Leave floating. |+| 21 | DVDD | power_in | Digital supply voltage, 3.0-3.6 V. Second DVDD pin; tie to same rail as pin 5. |+| 22 | DCOM | power_in | Digital ground return; tie to same ground as pin 4. |+| 23 | MSB-P2B11 | input | Port 2 parallel data input, bit DB11 (MSB). |+| 24 | P2B10 | input | Port 2 parallel data input, bit DB10. |+| 25 | P2B9 | input | Port 2 parallel data input, bit DB9. |+| 26 | P2B8 | input | Port 2 parallel data input, bit DB8. |+| 27 | P2B7 | input | Port 2 parallel data input, bit DB7. |+| 28 | P2B6 | input | Port 2 parallel data input, bit DB6. |+| 29 | P2B5 | input | Port 2 parallel data input, bit DB5. |+| 30 | P2B4 | input | Port 2 parallel data input, bit DB4. |+| 31 | P2B3 | input | Port 2 parallel data input, bit DB3. |+| 32 | P2B2 | input | Port 2 parallel data input, bit DB2. |+| 33 | P2B1 | input | Port 2 parallel data input, bit DB1. |+| 34 | P2B0-LSB | input | Port 2 parallel data input, bit DB0 (LSB). |+| 35 | RESERVED | unconnected | Reserved - no user connection. Leave floating. |+| 36 | RESERVED | unconnected | Reserved - no user connection. Leave floating. |+| 37 | DIV0 | input | Control input for PLL divider and input-port selector mode (see Table I/II of datasheet). |+| 38 | DIV1 | input | Control input for PLL divider and input-port selector mode (see Table I/II of datasheet). |+| 39 | REFIO | bidirectional | Reference input/output. Sources the 1.20 V internal band-gap reference (1.14-1.26 V, ~100 nA drive) or accepts an external reference (0.1-1.25 V, R_in ≈ 1 MΩ). Bypass with 0.1 µF to ACOM when using internal reference. |+| 40 | FSADJ | passive | Full-scale output current adjust. Connect R_SET (typ. 2 kΩ) to ACOM; I_OUTFS = 32 × I_REF, giving 2-20 mA full-scale. |+| 41 | AVDD | power_in | Analog supply voltage, 3.0-3.6 V (3.3 V nom). Analog supply current I_AVDD ≈ 33 mA typ. |+| 42 | IOUTB | output | Complementary differential DAC current output. Full-scale 2-20 mA; output compliance −1.0 V to +1.25 V; output resistance ≈100 kΩ, C ≈ 5 pF. |+| 43 | IOUTA | output | Differential DAC current output. Full-scale 2-20 mA; output compliance −1.0 V to +1.25 V. |+| 44 | ACOM | power_in | Analog ground return for AVDD and DAC current outputs. |+| 45 | CLKCOM | power_in | Clock and PLL common (ground return for CLKVDD/PLLVDD). |+| 46 | LPF | passive | Phase-locked loop loop-filter pin. Connect external RC filter to PLLCOM. |+| 47 | PLLVDD | power_in | PLL supply voltage, 3.0-3.6 V. Tie to CLKCOM/PLLCOM ground to disable the internal PLL. I_PLLVDD ≈ 4.5 mA typ. |+| 48 | CLKVDD | power_in | Clock supply voltage, 3.0-3.6 V. Powers the clock receiver. I_CLKVDD ≈ 10 mA typ. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LQFP-48(7x7) |+| Category | Data Acquisition |+| Pins | 48 |++## Ordering variants++Same part, different packaging or reel option.++- `AD9753ASTZRL`+- `AD9753ASTZRLASTRL`++## CAD (KiCad official)++- Symbol: `AD9753ASTZRL`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886597005676544) (28 pp, sha256 `c273731289795a16`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad9753astzrl-datasheet.pdf)