component
AD9753ASTZRL
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Analog Devices Digital To Analog Converters (DAC), LQFP-48(7x7). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+366−8@@ -1,13 +1,376 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ad9753astzrl",+ "title": "AD9753ASTZRL",+ "brief": "Analog Devices Digital To Analog Converters (DAC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Analog Devices Digital To Analog Converters (DAC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "data acquisition", "ad9753astzrl" ],+ "component": {+ "mpn": "AD9753ASTZRL",+ "manufacturer": "Analog Devices",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886597005676544",+ "parts": {+ "symbol": "ad9753astzrl.kicad_sym",+ "footprint": "ad9753astzrl.kicad_mod",+ "model_3d": "ad9753astzrl.glb",+ "model_3d_step": "ad9753astzrl.step",+ "lbr": "ad9753astzrl.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "RESET",+ "type": "input",+ "description": "Internal clock divider reset (CMOS logic input, 0/3.3 V)."+ },+ {+ "number": "2",+ "name": "CLK+",+ "type": "input",+ "description": "Differential clock input, positive leg. Can also be driven single-ended. Input range 0-3 V, differential swing 0.5-1.5 V, common-mode 0.75-2.25 V. Minimum 6.25 MHz when PLL is enabled."+ },+ {+ "number": "3",+ "name": "CLK-",+ "type": "input",+ "description": "Differential clock input, negative leg. Complements CLK+ when driven differentially."+ },+ {+ "number": "4",+ "name": "DCOM",+ "type": "power_in",+ "description": "Digital ground return for DVDD."+ },+ {+ "number": "5",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply voltage, 3.0-3.6 V (3.3 V nom). Digital supply current I_DVDD \u2248 3.5 mA typ."+ },+ {+ "number": "6",+ "name": "PLLLOCK",+ "type": "output",+ "description": "Phase-locked loop lock indicator output. CMOS output; V_OH \u2265 3.0 V, V_OL \u2264 0.3 V."+ },+ {+ "number": "7",+ "name": "MSB-P1B11",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB11 (MSB). CMOS levels referenced to DVDD/DCOM."+ },+ {+ "number": "8",+ "name": "P1B10",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB10."+ },+ {+ "number": "9",+ "name": "P1B9",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB9."+ },+ {+ "number": "10",+ "name": "P1B8",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB8."+ },+ {+ "number": "11",+ "name": "P1B7",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB7."+ },+ {+ "number": "12",+ "name": "P1B6",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB6."+ },+ {+ "number": "13",+ "name": "P1B5",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB5."+ },+ {+ "number": "14",+ "name": "P1B4",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB4."+ },+ {+ "number": "15",+ "name": "P1B3",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB3."+ },+ {+ "number": "16",+ "name": "P1B2",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB2."+ },+ {+ "number": "17",+ "name": "P1B1",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB1."+ },+ {+ "number": "18",+ "name": "LSB-P1B0",+ "type": "input",+ "description": "Port 1 parallel data input, bit DB0 (LSB)."+ },+ {+ "number": "19",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved - no user connection. Leave floating."+ },+ {+ "number": "20",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved - no user connection. Leave floating."+ },+ {+ "number": "21",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital supply voltage, 3.0-3.6 V. Second DVDD pin; tie to same rail as pin 5."+ },+ {+ "number": "22",+ "name": "DCOM",+ "type": "power_in",+ "description": "Digital ground return; tie to same ground as pin 4."+ },+ {+ "number": "23",+ "name": "MSB-P2B11",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB11 (MSB)."+ },+ {+ "number": "24",+ "name": "P2B10",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB10."+ },+ {+ "number": "25",+ "name": "P2B9",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB9."+ },+ {+ "number": "26",+ "name": "P2B8",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB8."+ },+ {+ "number": "27",+ "name": "P2B7",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB7."+ },+ {+ "number": "28",+ "name": "P2B6",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB6."+ },+ {+ "number": "29",+ "name": "P2B5",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB5."+ },+ {+ "number": "30",+ "name": "P2B4",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB4."+ },+ {+ "number": "31",+ "name": "P2B3",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB3."+ },+ {+ "number": "32",+ "name": "P2B2",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB2."+ },+ {+ "number": "33",+ "name": "P2B1",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB1."+ },+ {+ "number": "34",+ "name": "P2B0-LSB",+ "type": "input",+ "description": "Port 2 parallel data input, bit DB0 (LSB)."+ },+ {+ "number": "35",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved - no user connection. Leave floating."+ },+ {+ "number": "36",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved - no user connection. Leave floating."+ },+ {+ "number": "37",+ "name": "DIV0",+ "type": "input",+ "description": "Control input for PLL divider and input-port selector mode (see Table I/II of datasheet)."+ },+ {+ "number": "38",+ "name": "DIV1",+ "type": "input",+ "description": "Control input for PLL divider and input-port selector mode (see Table I/II of datasheet)."+ },+ {+ "number": "39",+ "name": "REFIO",+ "type": "bidirectional",+ "description": "Reference input/output. Sources the 1.20 V internal band-gap reference (1.14-1.26 V, ~100 nA drive) or accepts an external reference (0.1-1.25 V, R_in \u2248 1 M\u03a9). Bypass with 0.1 \u00b5F to ACOM when using internal reference."+ },+ {+ "number": "40",+ "name": "FSADJ",+ "type": "passive",+ "description": "Full-scale output current adjust. Connect R_SET (typ. 2 k\u03a9) to ACOM; I_OUTFS = 32 \u00d7 I_REF, giving 2-20 mA full-scale."+ },+ {+ "number": "41",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply voltage, 3.0-3.6 V (3.3 V nom). Analog supply current I_AVDD \u2248 33 mA typ."+ },+ {+ "number": "42",+ "name": "IOUTB",+ "type": "output",+ "description": "Complementary differential DAC current output. Full-scale 2-20 mA; output compliance \u22121.0 V to +1.25 V; output resistance \u2248100 k\u03a9, C \u2248 5 pF."+ },+ {+ "number": "43",+ "name": "IOUTA",+ "type": "output",+ "description": "Differential DAC current output. Full-scale 2-20 mA; output compliance \u22121.0 V to +1.25 V."+ },+ {+ "number": "44",+ "name": "ACOM",+ "type": "power_in",+ "description": "Analog ground return for AVDD and DAC current outputs."+ },+ {+ "number": "45",+ "name": "CLKCOM",+ "type": "power_in",+ "description": "Clock and PLL common (ground return for CLKVDD/PLLVDD)."+ },+ {+ "number": "46",+ "name": "LPF",+ "type": "passive",+ "description": "Phase-locked loop loop-filter pin. Connect external RC filter to PLLCOM."+ },+ {+ "number": "47",+ "name": "PLLVDD",+ "type": "power_in",+ "description": "PLL supply voltage, 3.0-3.6 V. Tie to CLKCOM/PLLCOM ground to disable the internal PLL. I_PLLVDD \u2248 4.5 mA typ."+ },+ {+ "number": "48",+ "name": "CLKVDD",+ "type": "power_in",+ "description": "Clock supply voltage, 3.0-3.6 V. Powers the clock receiver. I_CLKVDD \u2248 10 mA typ."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886597005676544",+ "pages": 28,+ "sha256": "c273731289795a16",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Analog Devices",+ "Package": "LQFP-48(7x7)",+ "Category": "Data Acquisition",+ "Pins": "48"+ }+ },+ "variants": [+ {+ "mpn": "AD9753ASTZRL",+ "kind": "packaging"+ },+ {+ "mpn": "AD9753ASTZRLASTRL",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ad9753astzrl"+ ],+ "discovery_pitch": "AD9753ASTZRL (Analog Devices) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +388,5 @@ "docs/ad9753astzrl-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }