AD9518-3ABCPZ-RL7

@@ -0,0 +1,90 @@+# AD9518-3ABCPZ-RL7++**Analog Devices** · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-48(7x7)++AD9518-3ABCPZ-RL7 from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | REFMON | output | Reference Monitor Output (3.3 V CMOS). Multiplexed status/monitor output configurable via register 0x01B. |+| 2 | LD | output | Lock Detect Output (3.3 V CMOS). Multiplexed selectable output configured via register 0x01A. |+| 3 | VCP | power_in | Charge Pump Power Supply. V_S ≤ V_CP ≤ 5.0 V; typically 3.3 V, but must be 5 V when a 5 V external VCXO is used. |+| 4 | CP | output | Charge Pump Output. Connects to the external PLL loop filter; nominal I_CP = 4.8 mA with CPRSET = 5.1 kΩ. |+| 5 | STATUS | output | Status Output (3.3 V CMOS). Multiplexed selectable output configured via register 0x017. |+| 6 | REF_SEL | input | Reference Select (3.3 V CMOS). Selects REF1 (low) or REF2 (high). Internal 30 kΩ pull-down. |+| 7 | SYNC | input | Manual Synchronization / Manual Holdover (3.3 V CMOS, active low). Initiates manual sync/holdover. Internal 30 kΩ pull-up. |+| 8 | LF | passive | Loop Filter Input. Connects to the internal VCO control voltage node. |+| 9 | BYPASS | passive | Internal LDO Bypass. Connect a 220 nF capacitor to ground for LDO stability. Contains ~31 pF of internal capacitance which may influence loop filter design at large loop bandwidths. |+| 10 | VS | power_in | 3.3 V Power Supply Pin (V_S = 3.135 V to 3.465 V). |+| 11 | CLK | input | Self-biased differential clock input (positive) for the clock distribution section. May be left floating if the internal VCO is used. |+| 12 | CLK_N | input | Self-biased differential clock input (negative, CLK-bar). May be left floating if the internal VCO is used. |+| 13 | SCLK | input | Serial Control Port Data Clock (3.3 V CMOS). |+| 14 | CS | input | Serial Control Port Chip Select (3.3 V CMOS, active low). Internal 30 kΩ pull-up. |+| 15 | SDO | output | Serial Control Port unidirectional serial data output (3.3 V CMOS). |+| 16 | SDIO | bidirectional | Serial Control Port bidirectional serial data input/output (3.3 V CMOS). |+| 17 | RESET | input | Chip Reset (3.3 V CMOS, active low). Internal 30 kΩ pull-up. |+| 18 | PD | input | Chip Power Down (3.3 V CMOS, active low). Internal 30 kΩ pull-up. |+| 19 | OUT4 | output | LVPECL Output (positive) - one side of the differential OUT4 pair. |+| 20 | OUT4_N | output | LVPECL Output (negative, OUT4-bar) - one side of the differential OUT4 pair. |+| 21 | VS_LVPECL | power_in | Extended-voltage LVPECL power supply pin (2.5 V to 3.3 V nominal). |+| 22 | OUT5 | output | LVPECL Output (positive) - one side of the differential OUT5 pair. |+| 23 | OUT5_N | output | LVPECL Output (negative, OUT5-bar) - one side of the differential OUT5 pair. |+| 24 | VS | power_in | 3.3 V Power Supply Pin. |+| 25 | VS | power_in | 3.3 V Power Supply Pin. |+| 26 | VS | power_in | 3.3 V Power Supply Pin. |+| 27 | GND | power_in | Ground. Also see the EPAD description. |+| 28 | OUT3_N | output | LVPECL Output (negative, OUT3-bar) - one side of the differential OUT3 pair. |+| 29 | OUT3 | output | LVPECL Output (positive) - one side of the differential OUT3 pair. |+| 30 | VS_LVPECL | power_in | Extended-voltage LVPECL power supply pin (2.5 V to 3.3 V nominal). |+| 31 | VS_LVPECL | power_in | Extended-voltage LVPECL power supply pin (2.5 V to 3.3 V nominal). |+| 32 | OUT2_N | output | LVPECL Output (negative, OUT2-bar) - one side of the differential OUT2 pair. |+| 33 | OUT2 | output | LVPECL Output (positive) - one side of the differential OUT2 pair. |+| 34 | GND | power_in | Ground. Also see the EPAD description. |+| 35 | VS | power_in | 3.3 V Power Supply Pin. |+| 36 | NC | unconnected | No connect. Leave floating. |+| 37 | VS | power_in | 3.3 V Power Supply Pin. |+| 38 | OUT1_N | output | LVPECL Output (negative, OUT1-bar) - one side of the differential OUT1 pair. |+| 39 | OUT1 | output | LVPECL Output (positive) - one side of the differential OUT1 pair. |+| 40 | VS_LVPECL | power_in | Extended-voltage LVPECL power supply pin (2.5 V to 3.3 V nominal). |+| 41 | OUT0_N | output | LVPECL Output (negative, OUT0-bar) - one side of the differential OUT0 pair. |+| 42 | OUT0 | output | LVPECL Output (positive) - one side of the differential OUT0 pair. |+| 43 | VS | power_in | 3.3 V Power Supply Pin. |+| 44 | RSET | passive | Bias current setting resistor. Connect a 4.12 kΩ resistor to ground to set the internal bias currents. |+| 45 | VS | power_in | 3.3 V Power Supply Pin. |+| 46 | CPRSET | passive | Charge pump current-set resistor. Connect a 5.1 kΩ resistor (range 2.7 to 10 kΩ) to ground to set the CP current range (I_CP = 3.06/CPRSET). |+| 47 | REFIN_N | input | Self-biased differential input for the PLL reference (negative, REFIN-bar). Alternatively serves as a single-ended CMOS input for REF2. |+| 48 | REFIN | input | Self-biased differential input for the PLL reference (positive, REFIN/REF1). Alternatively serves as a single-ended CMOS input for REF1. |+| EPAD | GND | power_in | Exposed thermal pad on the bottom of the package. Must be connected to ground for proper electrical and thermal operation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-48(7x7) |+| Category | Clock/Timing |+| Pins | 49 |++## Ordering variants++Same part, different packaging or reel option.++- `AD9518-3ABCPZ-RL7`++## CAD (KiCad official)++- Symbol: `AD9518-3ABCPZ-RL7`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589800267123494912) (64 pp, sha256 `ad1d5d3ef813be27`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad9518-3abcpz-rl7-datasheet.pdf)