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AD7951BSTZ
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Analog Devices Analog To Digital Converters (ADCs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# AD7951BSTZ++**Analog Devices** · Analog To Digital Converters (ADCs) · LQFP-48(7x7)++AD7951BSTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog power ground reference for all analog I/O maintained within ±0.3V of DGND and OGND potentials. |+| 2 | AVDD | power_in | Analog power supply nominally 4.75V to 5.25V with 10µF and 100nF decoupling capacitors required. |+| 3 | AGND | power_in | Analog power ground pin; ground reference for all analog I/O at same potential as DGND and OGND within ±0.3V. |+| 4 | BYTESWAP | input | Parallel mode selection (8-bit/14-bit) where low outputs LSB on D[7:0] and MSB on D[13:8], high swaps byte positions. |+| 5 | OB/2C | input | Output coding selection where high produces straight binary output and low produces twos complement from internal shift register. |+| 6 | WARP | input | Conversion mode selection used with IMPULSE pin where high/low selects warp mode for 1 MSPS operation. |+| 7 | IMPULSE | input | Conversion mode selection used with WARP pin where high/low selects impulse mode for lowest power dissipation at 670 kSPS. |+| 8 | SER/PAR | input | Serial/parallel interface selection where low selects parallel mode and high selects serial modes with data bits as high-impedance. |+| 9 | NC | unconnected | No connect pin; should not be connected to any signal. |+| 10 | NC | unconnected | No connect pin; should not be connected to any signal. |+| 11 | D0/DIVSCLK[0] | bidirectional | Data bit 0 in parallel mode or serial data clock division select in master read-after-convert mode to slow internally generated clock. |+| 12 | D1/DIVSCLK[1] | bidirectional | Data bit 1 in parallel mode or serial data clock division select in master read-after-convert mode used with DIVSCLK[0]. |+| 13 | D2/EXT/INT | bidirectional | Data bit 2 in parallel mode or serial clock source select where low = internal master clock and high = external slave clock. |+| 14 | D3/INVSYNC | bidirectional | Data bit 3 in parallel mode or serial SYNC invert select where low = SYNC active high and high = SYNC active low. |+| 15 | D4/INVSCLK | bidirectional | Data bit 4 in parallel mode or invert serial clock select where low uses rising edge and high uses falling edge of SDCLK/SCCLK. |+| 16 | D5/RDC/SDIN | bidirectional | Data bit 5 in parallel mode or read-during-convert select in master mode (high) or serial data input in slave mode for daisy-chain. |+| 17 | OGND | power_in | Input/output interface digital power ground reference for digital outputs maintained at same potential as AGND and DGND. |+| 18 | OVDD | power_in | Input/output interface digital supply nominally 2.7V to 5.5V matching host logic level with 10µF and 100nF decoupling. |+| 19 | DVDD | power_in | Digital power supply nominally 4.75V to 5.25V with 10µF and 100nF decoupling, can be supplied from AVDD through RC filter. |+| 20 | DGND | power_in | Digital power ground reference for digital circuits maintained within ±0.3V of AGND and OGND potentials. |+| 21 | D6/SDOUT | tri_state | Data bit 6 in parallel mode or serial data output in all serial modes shifting 14-bit conversion MSB first with high-impedance when CS or RD is high. |+| 22 | D7/SDCLK | bidirectional | Data bit 7 in parallel mode or serial data clock generating internal clock in master mode (EXT/INT = low) or accepting external clock in slave mode. |+| 23 | D8/SYNC | tri_state | Data bit 8 in parallel mode or serial frame synchronization output in master mode indicating valid SDOUT data with high-impedance when disabled. |+| 24 | D9/RDERROR | tri_state | Data bit 9 in parallel mode or serial read error flag in slave mode pulsing high if conversion completes before incomplete data read. |+| 25 | D10/HW/SW | bidirectional | Data bit 10 in parallel mode or hardware/software configuration select where low enables serial configuration register and high enables hardware pin configuration. |+| 26 | D11/SCIN | bidirectional | Data bit 11 in parallel mode or serial configuration data input in software mode accepting configuration data MSB first synchronized with SCCLK. |+| 27 | D12/SCCLK | bidirectional | Data bit 12 in parallel mode or serial configuration clock in software mode clocking in configuration data on active edge determined by INVSCLK. |+| 28 | D13/SCCS | bidirectional | Data bit 13 in parallel mode or serial configuration chip select in software mode enabling serial configuration port when low. |+| 29 | BUSY | tri_state | Busy output transitioning high when conversion starts and remaining high until conversion complete and data latched, with falling edge indicating data ready and high-impedance when disabled. |+| 30 | TEN | input | Input range select for 10V ranges used with BIPOLAR pin where low = 5V ranges and high = 10V ranges. |+| 31 | RD | input | Read data enable that with CS both low enables parallel output bus or gates external clock in slave serial mode. |+| 32 | CS | input | Chip select that with RD both low enables parallel output bus or gates external clock in slave serial mode for multicircuit applications. |+| 33 | RESET | input | Reset input where rising edge aborts current conversion and tristates data bus, and falling edge resets ADC clearing data outputs and configuration register. |+| 34 | PD | input | Power-down input where high powers down ADC reducing supply currents to 10µW typical while inhibiting conversions but keeping digital interface active. |+| 35 | CNVST | input | Conversion start input where falling edge puts sample-and-hold into hold state and initiates conversion; requires fast clean edges with minimal jitter. |+| 36 | BIPOLAR | input | Input range select for bipolar/unipolar modes used with TEN pin where low = unipolar ranges and high = bipolar (±) ranges. |+| 37 | REF | bidirectional | Reference input/output producing 5V when internal reference enabled (PDREF/PDBUF = low) or accepting external reference up to AVDD+0.1V when disabled with 22µF minimum decoupling. |+| 38 | REFGND | power_in | Reference input analog ground providing low impedance return path for reference circuits connected to analog ground plane with short thick traces. |+| 39 | IN− | input | Analog input ground sense negative input of differential pair connected to analog ground plane or remote sense for common-mode rejection. |+| 40 | VCC | power_in | High voltage positive supply nominally +7V to +15V providing positive supply for analog converter circuits, must exceed maximum input by minimum 2V. |+| 41 | VEE | power_in | High voltage negative supply nominally 0V to −15V (0V for unipolar ranges) providing negative supply for bipolar converter, must be below minimum input by 2V. |+| 42 | AGND | power_in | Analog power ground pin serving as ground reference for analog I/O maintained within ±0.3V of DGND and OGND. |+| 43 | IN+ | input | Analog input signal referenced to IN− and sampled on falling edge of CNVST over voltage range of −0.1V to AVDD+0.1V. |+| 44 | AVDD | power_in | Analog power supply nominally 4.75V to 5.25V sequenced before or simultaneously with DVDD requiring 10µF and 100nF decoupling capacitors. |+| 45 | TEMP | output | Temperature sensor analog output providing 311mV nominal at 25°C with 1mV/°C temperature sensitivity enabled when internal reference on (PDREF=PDBUF=low). |+| 46 | REFBUFIN | input | Reference buffer input accepting 2.5V to produce 5V output on REF pin when using external reference with internal buffer enabled (PDBUF = low, PDREF = high). |+| 47 | PDREF | input | Internal reference power-down input where low enables on-chip 5V reference with ±3ppm/°C drift and high disables reference for external operation. |+| 48 | PDBUF | input | Internal reference buffer power-down input where low enables internal buffer and high powers down buffer (must be low when using internal reference). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LQFP-48(7x7) |+| Category | ADC/DAC/Data Conversion |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `AD7951BSTZ`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `ad7951bstz-etched.step` / `ad7951bstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7951bstz.step` / `ad7951bstz.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886774881914880) (32 pp, sha256 `3a779927e1183cb4`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad7951bstz-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "ad7951bstz",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ad7951bstz.kicad_sym",+ "ad7951bstz.kicad_mod",+ "ad7951bstz.glb",+ "ad7951bstz.step",+ "ad7951bstz.lbr",+ "docs/hero.png",+ "docs/ad7951bstz-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "AD7951BSTZ",+ "manufacturer": "Analog Devices",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Analog To Digital Converters (ADCs)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886774881914880",+ "parts": {+ "symbol": "ad7951bstz.kicad_sym",+ "footprint": "ad7951bstz.kicad_mod",+ "model_3d": "ad7951bstz-etched.glb",+ "model_3d_plain": "ad7951bstz.glb",+ "model_3d_step": "ad7951bstz-etched.step",+ "model_3d_step_plain": "ad7951bstz.step",+ "lbr": "ad7951bstz.lbr"+ },+ "distributor_links": {+ "lcsc": "C578572"+ },+ "pins": [+ {+ "number": "1",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog power ground reference for all analog I/O maintained within ±0.3V of DGND and OGND potentials."+ },+ {+ "number": "2",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply nominally 4.75V to 5.25V with 10µF and 100nF decoupling capacitors required."+ },+ {+ "number": "3",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog power ground pin; ground reference for all analog I/O at same potential as DGND and OGND within ±0.3V."+ },+ {+ "number": "4",+ "name": "BYTESWAP",+ "type": "input",+ "description": "Parallel mode selection (8-bit/14-bit) where low outputs LSB on D[7:0] and MSB on D[13:8], high swaps byte positions."+ },+ {+ "number": "5",+ "name": "OB/2C",+ "type": "input",+ "description": "Output coding selection where high produces straight binary output and low produces twos complement from internal shift register."+ },+ {+ "number": "6",+ "name": "WARP",+ "type": "input",+ "description": "Conversion mode selection used with IMPULSE pin where high/low selects warp mode for 1 MSPS operation."+ },+ {+ "number": "7",+ "name": "IMPULSE",+ "type": "input",+ "description": "Conversion mode selection used with WARP pin where high/low selects impulse mode for lowest power dissipation at 670 kSPS."+ },+ {+ "number": "8",+ "name": "SER/PAR",+ "type": "input",+ "description": "Serial/parallel interface selection where low selects parallel mode and high selects serial modes with data bits as high-impedance."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; should not be connected to any signal."+ },+ {+ "number": "10",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; should not be connected to any signal."+ },+ {+ "number": "11",+ "name": "D0/DIVSCLK[0]",+ "type": "bidirectional",+ "description": "Data bit 0 in parallel mode or serial data clock division select in master read-after-convert mode to slow internally generated clock."+ },+ {+ "number": "12",+ "name": "D1/DIVSCLK[1]",+ "type": "bidirectional",+ "description": "Data bit 1 in parallel mode or serial data clock division select in master read-after-convert mode used with DIVSCLK[0]."+ },+ {+ "number": "13",+ "name": "D2/EXT/INT",+ "type": "bidirectional",+ "description": "Data bit 2 in parallel mode or serial clock source select where low = internal master clock and high = external slave clock."+ },+ {+ "number": "14",+ "name": "D3/INVSYNC",+ "type": "bidirectional",+ "description": "Data bit 3 in parallel mode or serial SYNC invert select where low = SYNC active high and high = SYNC active low."+ },+ {+ "number": "15",+ "name": "D4/INVSCLK",+ "type": "bidirectional",+ "description": "Data bit 4 in parallel mode or invert serial clock select where low uses rising edge and high uses falling edge of SDCLK/SCCLK."+ },+ {+ "number": "16",+ "name": "D5/RDC/SDIN",+ "type": "bidirectional",+ "description": "Data bit 5 in parallel mode or read-during-convert select in master mode (high) or serial data input in slave mode for daisy-chain."+ },+ {+ "number": "17",+ "name": "OGND",+ "type": "power_in",+ "description": "Input/output interface digital power ground reference for digital outputs maintained at same potential as AGND and DGND."+ },+ {+ "number": "18",+ "name": "OVDD",+ "type": "power_in",+ "description": "Input/output interface digital supply nominally 2.7V to 5.5V matching host logic level with 10µF and 100nF decoupling."+ },+ {+ "number": "19",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply nominally 4.75V to 5.25V with 10µF and 100nF decoupling, can be supplied from AVDD through RC filter."+ },+ {+ "number": "20",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital power ground reference for digital circuits maintained within ±0.3V of AGND and OGND potentials."+ },+ {+ "number": "21",+ "name": "D6/SDOUT",+ "type": "tri_state",+ "description": "Data bit 6 in parallel mode or serial data output in all serial modes shifting 14-bit conversion MSB first with high-impedance when CS or RD is high."+ },+ {+ "number": "22",+ "name": "D7/SDCLK",+ "type": "bidirectional",+ "description": "Data bit 7 in parallel mode or serial data clock generating internal clock in master mode (EXT/INT = low) or accepting external clock in slave mode."+ },+ {+ "number": "23",+ "name": "D8/SYNC",+ "type": "tri_state",+ "description": "Data bit 8 in parallel mode or serial frame synchronization output in master mode indicating valid SDOUT data with high-impedance when disabled."+ },+ {+ "number": "24",+ "name": "D9/RDERROR",+ "type": "tri_state",+ "description": "Data bit 9 in parallel mode or serial read error flag in slave mode pulsing high if conversion completes before incomplete data read."+ },+ {+ "number": "25",+ "name": "D10/HW/SW",+ "type": "bidirectional",+ "description": "Data bit 10 in parallel mode or hardware/software configuration select where low enables serial configuration register and high enables hardware pin configuration."+ },+ {+ "number": "26",+ "name": "D11/SCIN",+ "type": "bidirectional",+ "description": "Data bit 11 in parallel mode or serial configuration data input in software mode accepting configuration data MSB first synchronized with SCCLK."+ },+ {+ "number": "27",+ "name": "D12/SCCLK",+ "type": "bidirectional",+ "description": "Data bit 12 in parallel mode or serial configuration clock in software mode clocking in configuration data on active edge determined by INVSCLK."+ },+ {+ "number": "28",+ "name": "D13/SCCS",+ "type": "bidirectional",+ "description": "Data bit 13 in parallel mode or serial configuration chip select in software mode enabling serial configuration port when low."+ },+ {+ "number": "29",+ "name": "BUSY",+ "type": "tri_state",+ "description": "Busy output transitioning high when conversion starts and remaining high until conversion complete and data latched, with falling edge indicating data ready and high-impedance when disabled."+ },+ {+ "number": "30",+ "name": "TEN",+ "type": "input",+ "description": "Input range select for 10V ranges used with BIPOLAR pin where low = 5V ranges and high = 10V ranges."+ },+ {+ "number": "31",+ "name": "RD",+ "type": "input",+ "description": "Read data enable that with CS both low enables parallel output bus or gates external clock in slave serial mode."+ },+ {+ "number": "32",+ "name": "CS",+ "type": "input",+ "description": "Chip select that with RD both low enables parallel output bus or gates external clock in slave serial mode for multicircuit applications."+ },+ {+ "number": "33",+ "name": "RESET",+ "type": "input",+ "description": "Reset input where rising edge aborts current conversion and tristates data bus, and falling edge resets ADC clearing data outputs and configuration register."+ },+ {+ "number": "34",+ "name": "PD",+ "type": "input",+ "description": "Power-down input where high powers down ADC reducing supply currents to 10µW typical while inhibiting conversions but keeping digital interface active."+ },+ {+ "number": "35",+ "name": "CNVST",+ "type": "input",+ "description": "Conversion start input where falling edge puts sample-and-hold into hold state and initiates conversion; requires fast clean edges with minimal jitter."+ },+ {+ "number": "36",+ "name": "BIPOLAR",+ "type": "input",+ "description": "Input range select for bipolar/unipolar modes used with TEN pin where low = unipolar ranges and high = bipolar (±) ranges."+ },+ {+ "number": "37",+ "name": "REF",+ "type": "bidirectional",+ "description": "Reference input/output producing 5V when internal reference enabled (PDREF/PDBUF = low) or accepting external reference up to AVDD+0.1V when disabled with 22µF minimum decoupling."+ },+ {+ "number": "38",+ "name": "REFGND",+ "type": "power_in",+ "description": "Reference input analog ground providing low impedance return path for reference circuits connected to analog ground plane with short thick traces."+ },+ {+ "number": "39",+ "name": "IN−",+ "type": "input",+ "description": "Analog input ground sense negative input of differential pair connected to analog ground plane or remote sense for common-mode rejection."+ },+ {+ "number": "40",+ "name": "VCC",+ "type": "power_in",+ "description": "High voltage positive supply nominally +7V to +15V providing positive supply for analog converter circuits, must exceed maximum input by minimum 2V."+ },+ {+ "number": "41",+ "name": "VEE",+ "type": "power_in",+ "description": "High voltage negative supply nominally 0V to −15V (0V for unipolar ranges) providing negative supply for bipolar converter, must be below minimum input by 2V."+ },+ {+ "number": "42",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog power ground pin serving as ground reference for analog I/O maintained within ±0.3V of DGND and OGND."+ },+ {+ "number": "43",+ "name": "IN+",+ "type": "input",+ "description": "Analog input signal referenced to IN− and sampled on falling edge of CNVST over voltage range of −0.1V to AVDD+0.1V."+ },+ {+ "number": "44",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply nominally 4.75V to 5.25V sequenced before or simultaneously with DVDD requiring 10µF and 100nF decoupling capacitors."+ },+ {+ "number": "45",+ "name": "TEMP",+ "type": "output",+ "description": "Temperature sensor analog output providing 311mV nominal at 25°C with 1mV/°C temperature sensitivity enabled when internal reference on (PDREF=PDBUF=low)."+ },+ {+ "number": "46",+ "name": "REFBUFIN",+ "type": "input",+ "description": "Reference buffer input accepting 2.5V to produce 5V output on REF pin when using external reference with internal buffer enabled (PDBUF = low, PDREF = high)."+ },+ {+ "number": "47",+ "name": "PDREF",+ "type": "input",+ "description": "Internal reference power-down input where low enables on-chip 5V reference with ±3ppm/°C drift and high disables reference for external operation."+ },+ {+ "number": "48",+ "name": "PDBUF",+ "type": "input",+ "description": "Internal reference buffer power-down input where low enables internal buffer and high powers down buffer (must be low when using internal reference)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins 9-10 listed as type 'DO' (Digital Output) in datasheet Table 6 but described as 'NC' (No Connec"+ ],+ "pages_sent": 32,+ "cost_usd": 0.703,+ "at": "2026-09-21T21:21:44"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886774881914880",+ "pages": 32,+ "sha256": "3a779927e1183cb4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}