AD7622BSTZ

@@ -0,0 +1,92 @@+# AD7622BSTZ++**Analog Devices** · Analog To Digital Converters (ADCs) · LQFP-48(7x7)++AD7622BSTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog power ground. |+| 2 | AVDD | power_in | Input analog power pin. Nominally 2.5 V. |+| 3 | DGND | power_in | Digital power ground. |+| 4 | BYTESWAP | input | Parallel mode selection (8-bit/16-bit). When high, LSB is output on D[15:8] and MSB is output on D[7:0]; when low, LSB is on D[7:0] and MSB is on D[15:8]. |+| 5 | OB/2C | input | Straight binary/binary twos complement output select. High = straight binary; low = twos complement (MSB inverted). |+| 6 | WARP | input | Conversion mode selection. WARP=high with NORMAL=high selects wideband warp mode; WARP=high with NORMAL=low selects warp mode. Fastest modes; minimum conversion rate must be respected. |+| 7 | NORMAL | input | Conversion mode selection (active low). When NORMAL=low and WARP=low, selects normal mode with full accuracy independent of the minimum conversion rate. |+| 8 | SER/PAR | input | Serial/parallel interface selection input. High = serial mode; low = parallel port selected. |+| 9 | D0 | output | Bit 0 of the parallel port data output bus. Always an output regardless of interface mode. |+| 10 | D1 | output | Bit 1 of the parallel port data output bus. Always an output regardless of interface mode. |+| 11 | D2/DIVSCLK[0] | bidirectional | Parallel mode: Bit 2 of the data output bus. Serial mode (SER/PAR=high) with master serial read-after-convert (EXT/INT=low, RDC/SDIN=low): serial clock division select bit 0 used to slow the internally generated serial clock. |+| 12 | D3/DIVSCLK[1] | bidirectional | Parallel mode: Bit 3 of the data output bus. Serial master read-after-convert mode: serial clock division select bit 1. |+| 13 | D4/EXT/INT | bidirectional | Parallel mode: Bit 4 of the data output bus. Serial mode (SER/PAR=high): serial clock source select - low = master (internal SCLK), high = slave (external SCLK gated by CS). |+| 14 | D5/INVSYNC | bidirectional | Parallel mode: Bit 5 of the data output bus. Serial master mode (EXT/INT=low): selects active state of SYNC - low = SYNC active high, high = SYNC active low. |+| 15 | D6/INVSCLK | bidirectional | Parallel mode: Bit 6 of the data output bus. Serial mode (SER/PAR=high): inverts the SCLK signal in all serial modes. |+| 16 | D7/RDC/SDIN | bidirectional | Parallel mode: Bit 7 of the data output bus. Serial master (EXT/INT=low): RDC selects read-during-convert (high) or read-after-convert (low) mode. Serial slave (EXT/INT=high): SDIN serial data input for daisy-chaining ADCs (16 SCLK delay). |+| 17 | OGND | power_in | Input/output interface digital power ground. |+| 18 | OVDD | power_in | Input/output interface digital power. Nominally at the same supply as the host interface (2.5 V or 3 V, spec range 2.3 V to 3.6 V). |+| 19 | DVDD | power_in | Digital power. Nominally 2.5 V. |+| 20 | DGND | power_in | Digital power ground. |+| 21 | D8/SDOUT | output | Parallel mode: Bit 8 of the data output bus. Serial mode (SER/PAR=high): serial data output synchronized to SCLK, MSB-first from an on-chip 16-bit shift register. Format set by OB/2C. |+| 22 | D9/SCLK | bidirectional | Parallel mode: Bit 9 of the data output bus. Serial mode: serial data clock. Direction depends on EXT/INT (input in slave mode, output in master mode); active edge depends on INVSCLK. |+| 23 | D10/SYNC | output | Parallel mode: Bit 10 of the data output bus. Serial master mode (EXT/INT=low): SYNC frame synchronization output for use with the internal data clock. Polarity set by INVSYNC. |+| 24 | D11/RDERROR | output | Parallel mode: Bit 11 of the data output bus. Serial slave mode (EXT/INT=high): RDERROR read-error flag - pulsed high if a read is started but not completed when the next conversion completes (current data lost). |+| 25 | D12 | output | Bit 12 of the parallel port data output bus. Always an output regardless of interface mode. |+| 26 | D13 | output | Bit 13 of the parallel port data output bus. Always an output regardless of interface mode. |+| 27 | D14 | output | Bit 14 of the parallel port data output bus. Always an output regardless of interface mode. |+| 28 | D15 | output | Bit 15 of the parallel port data output bus (MSB). Always an output regardless of interface mode. |+| 29 | BUSY | output | Busy output. Transitions high when a conversion starts and remains high until the conversion is complete and data has been latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. |+| 30 | DGND | power_in | Digital power ground. |+| 31 | RD | input | Read data (active low). When CS and RD are both low, the parallel or serial output bus is enabled. |+| 32 | CS | input | Chip select (active low). When CS and RD are both low, the parallel or serial output bus is enabled. Also used to gate the external clock in slave serial mode. |+| 33 | RESET | input | Reset input (active high). When high, resets the AD7622 and aborts the current conversion. Falling edge enables calibration mode (BUSY pulses high). Tie to DGND if unused. |+| 34 | PD | input | Power-down input. When high, powers down the ADC (2 µW typical). Conversions are inhibited after the current one completes. |+| 35 | CNVST | input | Conversion start (active low). A falling edge on CNVST puts the internal sample-and-hold into hold and initiates a conversion. |+| 36 | AGND | power_in | Analog power ground. |+| 37 | REF | bidirectional | Reference output/input. With PDREF/PDBUF=low, internal reference and buffer are enabled producing 2.048 V on this pin. With PDREF/PDBUF=high, they are disabled and an external reference (up to AVDD) can be applied here. Requires decoupling. |+| 38 | REFGND | power_in | Reference input analog ground. |+| 39 | IN- | input | Differential negative analog input. Voltage range VIN+ − VIN− is ±VREF; operating input voltage referenced to AGND is −0.1 V to AVDD (external reference) or −0.1 V to VREF (internal reference). |+| 40 | NC | unconnected | No connect. |+| 41 | AGND | power_in | Analog power ground. |+| 42 | AGND | power_in | Analog power ground. |+| 43 | IN+ | input | Differential positive analog input. |+| 44 | AVDD | power_in | Input analog power pin. Nominally 2.5 V. |+| 45 | TEMP | output | Temperature sensor analog output. Nominally 278 mV @ 25°C with a temperature coefficient of 1 mV/°C. Output resistance ~4.7 kΩ. |+| 46 | REFBUFIN | bidirectional | Internal reference output / reference buffer input. With PDREF/PDBUF=low, produces the 1.2 V (typ) band-gap output (requires external decoupling) that feeds the internal buffer to generate 2.048 V on REF. With PDBUF=low, PDREF=high, applying 1.2 V here produces 2.048 V on REF. |+| 47 | PDREF | input | Internal reference power-down input. Low = internal reference enabled; high = internal reference powered down and an external reference must be used. |+| 48 | PDBUF | input | Internal reference buffer power-down input. Low = buffer enabled (must be low when using internal reference); high = buffer powered down. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LQFP-48(7x7) |+| Category | Analog ICs |+| Pins | 48 |++## Ordering variants++Same part, different packaging or reel option.++- `AD7622BSTZ`+- `AD7622BSTZRL`+- `AD7622BSTZBCPZ`+- `AD7622BSTZBCPZRL`++## CAD (KiCad official)++- Symbol: `AD7622BSTZ`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885740721197056) (28 pp, sha256 `421bd15f46f1c4ca`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad7622bstz-datasheet.pdf)